MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 60

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
3.13 SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master,
two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input).
The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register
(PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1
module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the
external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or
load data out to the internal data shift registers, as well as to increment the data FIFO.
.
60
Ref No.
1.
7
8
9
SCLK, MOSI, MISO
SCLK, MOSI, MISO
Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180 (Continued)
The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by
programming SPI_Control (0x00216138) register together with system clock.
Receive data setup time relative to falling edge of SPI_CLK
Receive data hold time relative to falling edge of SPI_CLK
SPI_CLK frequency, 50% duty cycle required
SPIRDY
SPIRDY
Figure 41. Master SPI Timing Diagram Using SPI_RDY Level Trigger
Figure 40. Master SPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SS
1
MC9328MX1 Advance Information, Rev. 4
2
Parameter
3
1
4
5
1
1
Minimum
15
15
–
Freescale Semiconductor
Maximum
20
–
–
MHz
Unit
ns
ns