MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 90

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold time and
setup time, according to:
Rising-edge latch data
In most of case, duty cycle is 50 / 50, therefore
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
Falling-edge latch data
3.22.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 71 on page 91 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 43 on page 91.
90
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
Ref No.
4
5
6
7
Table 42. Gated Clock Mode Timing Parameters (Continued)
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
MC9328MX1 Advance Information, Rev. 4
Parameter
Minimum
10.42
10.42
1
0
Maximum
48
–
–
–
MHz
Unit
ns
ns
ns
Freescale Semiconductor