MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 88

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

Specifications
3.22 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for statistic data
generation, a status register, interface logic, a 32
3.22.1 Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 69 on page 89 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 42 on page 89.
88
Ref
No.
28
29
30
31
32
33
34
1.
2.
3.
All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP =
0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 –
When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits
in the Clock controller module (CRM). By default, the input is selected from Port C alternate function.
STCK high to STXD high impedance
SRXD setup time before SRCK low
SRXD hole time after SRCK low
SRXD setup before STCK falling
SRXD hold after STCK falling
SRXD setup before STCK falling
SRXD hold after STCK falling
PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a.
bl = bit length; wl = word length
Synchronous External Clock Operation (Port B Alternate Function)
Synchronous Internal Clock Operation (Port B Alternate Function)
Parameter
Table 41. SSI 2 Timing Parameter Table (Continued)
MC9328MX1 Advance Information, Rev. 4
×
32 image data receive FIFO, and a 16
Minimum
18.81
17.90
1.14
1.14
0
0
0
1.8V +/- 0.10V
Maximum
29.75
–
–
–
–
–
–
Minimum
15.7
16.5
1.0
1.0
0
0
0
3.0V +/- 0.30V
2
2
×
Freescale Semiconductor
32 statistic data FIFO.
Maximum
26.1
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns