MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 27

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MC9328MX1/D

Manufacturer Part Number
MC9328MX1/D
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
3.9.2.3 DTACK Write Cycle without DMA
Freescale Semiconductor
Number
10
11
Databus
(output from MX1)
1
2
3
4
5
6
7
8
9
RW
OE
EB
CS5
Address
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
(logic high)
DTACK
CS5 assertion time
EB assertion time
CS5 pulse width
RW negated before CS5 is negated
RW negated to Address inactive
Data hold timing after RW negated
Data ready after CS5 is asserted
EB negated before CS5 is negated
DTACK pulse width
DTACK asserted after CS5 asserted
DTACK asserted to RW negated
(1)
(2)
Characteristic
(9)
programmable
min 0ns
programmable
min 0ns
Figure 8. DTACK Write Cycle without DMA
(6)
MC9328MX1 Advance Information, Rev. 4
(3)
(7)
(11)
See note 2.
See note 2
1.5T+0.58
0.5T+0.74
Minimum
1.5T-0.59
2T+1.8
57.31
3T
1T
(3.0 ± 0.3) V
(8)
(10)
(4)
Maximum
1.5T+1.58
0.5T+2.17
3T+5.26
1019T
3T
T
(5)
Specifications
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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