MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 25

• Manufacturer Part Number: MC9328MX1/D
• Description: i.MX Integrated Portable System Processor
• Manufacturer: ETC

3.9.2.2 DTACK Read Cycle DMA Enabled
Freescale Semiconductor
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
Note:
0. DTACK assert means DTACK become low level.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
10
RW
Databus
(input to MX1)
5
6
7
8
9
EB
CS5
OE
Address
(logic high)
DTACK
Data hold timing after OE negated
OE negated to CS negated
OE negated after EB negated
DTACK pulse width
DTACK asserted to OE negated
Data ready after DTACK asserted
(1)
Characteristic
programmable
min 0ns
(5)
Figure 7. DTACK Read Cycle DMA Enabled
MC9328MX1 Advance Information, Rev. 4
(2)
(11)
(6)
(8)
0.5T+0.24
Minimum
3T+2.2
0.5
1T
0
0
(10)
(3.0 ± 0.3) V
(4)
(3)
(7)
Maximum
0.5T+0.67
4T+6.86
1.5
3T
(9)
–
T
Specifications
Unit
ns
ns
ns
ns
ns
ns
25