MC9328MX1/D ETC, MC9328MX1/D Datasheet - Page 67

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MC9328MX1/D

Manufacturer Part Number
MC9328MX1/D
Description
i.MX Integrated Portable System Processor
Manufacturer
ETC
Datasheet
Figure 51 on page 68 shows the basic write operation timing. As with the read operation, after the card response,
the data transfer starts after N
transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a
transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned.
The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow
terminated by a stop transmission command.
Freescale Semiconductor
CMD
DAT
S T
Host Command
Content
Z****Z
CMD
CMD
DAT
DAT
WR
CRC
S T
S T
D D D D
cycles. The data is suffixed with CRC check bits to allow the card to check for
Figure 50. Timing Diagrams at Data Read
E Z Z P
Host Command
Host Command
Valid Read Data
Z Z P
Content
Content
MC9328MX1 Advance Information, Rev. 4
N
CR
N
Z****Z
AC
*****
cycles
******
cycles
******
N
ST
CRC
CRC
P S T
D D D D
P S D
E Z Z P
E Z Z P
Z Z P
N
N
N
E
Content
AC
CR
CR
Response
D D D
Z
Read Data
cycles
Z
cycles
******
******
cycles
******
Z
P S T
P S D
P S T
*****
CRC E Z
Timing of stop command
(CMD12, data transfer mode)
Timing of single block read
D D D
Content
Content
P
Read Data
Response
Response
*****
N
AC
*****
cycles
*****
CRC E Z
Timing of multiple block read
CRC E Z
P S D D D D
Read Data
*****
Specifications
67

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