S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 126

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

124
31.3.3
Asynchronous Write Timing Waveform in Synchronous Mode
31.3.3.1 Write Cycle (Address Latch Type)
MRS# = V
UB#, LB#
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
CLK
Address
CS#
WE#
Data in
Data out
ADV#
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for word operation.
A write ends at the earliest transition when CS# goes or and WE# goes high. The t
of write to the end of write.
t
t
t
Clock input does not have any affect to the write operation if the parameter t
Address Latch Type, UB#, LB# Controlled.
t
AW
CW
BW
WP(min)
Symbol
t
t
t
CSS(A)
t
AS(A)
AH(A)
t
t
ADV
is measured from the address valid to the end of write. In this address latch type write timing, t
is measured from the UB# and LB# going low to the end of write.
is measured from the CS# going low to the end of write.
CW
AW
Table 31.6 Asynchronous Write in Synchronous Mode AC Characteristics
= 70ns for continuous write operation over 50 times.
t
IH
AS(A)
, OE# = V
t
Valid
ADV
Figure 31.7 Timing Waveform Of Write Cycle (Low ADV# Type)
0
t
AS
Min
t
10
60
60
CSS(A)
7
0
7
1
t
AH(A)
IH
Speed
Read La tency 5
, WAIT# = High-Z, UB# and LB# Controlled
High-Z
2
A d v a n c e
t
S71WS-Nx0 Based MCPs
WLRL
Max
—
—
—
—
—
—
WP
3
) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
t
CW
4
t
AW
Units
t
t
BW
WP
ns
5
I n f o r m a t i o n
6
Symbol
t
WLRL
t
t
t
t
t
BW
DW
WP
DH
AS
7
8
t
DW
Dat a Valid
55
High-Z
WLRL
9
(Note
Min
60
30
is met.
1
0
0
10
WP
t
DH
Speed
is measured from the beginning
2)
S71WS-N_01_A4 September 15, 2005
11
12
Max
—
—
—
—
—
—
WC
13
is same as t
clock
Units
14
ns
ns
ns
AW
.