S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 75

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

September 15, 2005 S71WS-N_01_A4
14.8.2
Synchronous/Burst Read
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
3. The content in this document is Advance information for the S29WS128N. Content in this document is
JEDEC
Preliminary for the S29W256N.
Parameter
01 MHz < Freq. ≤ 14 MHz
14 MHz < Freq. ≤ 27 MHz
27 MHz < Freq. ≤ 40 MHz
40 MHz < Freq. ≤ 54 MHz
54 MHz < Freq. ≤ 67 MHz
67 MHz < Freq. ≤ 80 MHz
Standard
Max Frequency
t
t
t
t
A d v a n c e
t
t
t
t
t
t
t
t
t
f
BACC
RDYS
RACC
IACC
t
t
ACS
ACH
BDH
CEZ
OEZ
CES
CAS
AVC
AVD
CLK
CR
OE
Table 14.2 Synchronous Wait State Requirements
Latency
Burst Access Time Valid Clock to Output Delay
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time from Next Clock Cycle
Chip Enable to RDY Valid
Output Enable to Output Valid
Chip Enable to High Z
Output Enable to High Z
CE# Setup Time to CLK
RDY Setup Time to CLK
Ready Access Time from CLK
CE# Setup Time to AVD#
AVD# Low to CLK
AVD# Pulse
Minimum clock frequency
I n f o r m a t i o n
S71WS-Nx0 Based MCPs
Description
(Note
(Note
(Note
2)
(Note
2)
1)
1)
Wait State Requirement
2
3
4
5
6
7
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
54 MHz
13.5
13.5
13.5
13.5
5
7
4
5
1
66 MHz
11.2
11.2
11.2
80
10
10
4
1
4
0
4
8
11.2
4
6
3
80 MHz
3.5
9
9
9
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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