S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 139

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

September 15, 2005 S71WS-N_01_A4
32.3.4
Synchronous Burst Write Stop Timing Waveform
Latency = 5, Burst Length = 4, WP = Low enable (OE#= V
Notes:
1.
2.
3.
4.
LB#, UB#
CLK
ADV#
Address
CS#
WE#
Data in
WAIT#
The new burst operation can be issued only after the previous burst operation is finished.
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
The burst stop operation should not be repeated for over 2.5µs.
Symbol
t
t
t
BSADV
t
t
CSLH
CSHP
t
t
WES
WEH
BS
BH
A d v a n c e
WL
WH
t
t
AS(B)
CSS(B)
WZ
High-Z
or t
): Data available (driven by Latency-1 clock)
t
Figure 32.9 Timing Waveform of Burst Write Stop by CS#
): Data don’t care (driven by CS# high going edge)
WES
AWL
Valid
Min
12
0
t
7
5
5
5
5
5
t
WL
WEH
): Data not available (driven by CS# low going edge or ADV# low going edge)
Table 32.8 Burst Write Stop AC Characteristics
T
t
ADVS
Speed
t
ADVH
1
t
AH(B)
Latency 5
I n f o r m a t i o n
Max
S71WS-Nx0 Based MCPs
—
—
—
—
—
—
—
2
t
WH
Don’t Ca re
3
t
t
DS
Units
BS
ns
D0
4
t
t
BH
CSLH
D1
5
t
DHC
t
t
CSHP
t
t
BSADV
WZ
WHP
6
Symbol
t
t
t
t
t
t
WHP
DHC
WH
WL
WZ
DS
Valid
High-Z
7
IH
t
WL
, MRS# = V
8
Latency 5
Min
—
—
—
5
5
3
t
9
WH
Speed
IH
10
).
Max
10
12
—
—
—
7
11
D0
12
D1
Units
ns
13
D2
137