S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 145
S71WS256NC0BAWE32
Manufacturer Part Number
S71WS256NC0BAWE32
Description
Stacked Multi-Chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71WS256NC0BAWE32.pdf
(188 pages)
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September 15, 2005 S71WS-N_01_A4
Latency = 5, Burst Length = 4 (MRS# = V
Notes:
1.
2.
3.
4.
LB#, UB#
WE#
Data in
CLK
ADV#
Address
CS#
OE#
Data out
WAIT#
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
BEADV
Table 33.5 Asynchronous Write (Low ADV# Type) to Burst Read AC Characteristics
Symbol
t
BEADV
should be met.
Figure 33.5 Synchronous Burst Read to Synchronous Burst Write Timing
t
A d v a n c e
ADVS
t
AS(B)
High- Z
WL
WH
Valid
WZ
or t
): Data available (driven by Latency-1 clock)
0
t
WL
): Data don’t care (driven by CS# high going edge)
T
BC
AWL
High -Z
t
CSS(B)
Min
t
) should not be over 2.5µs.
1
ADVH
7
): Data not available (driven by CS# low going edge or ADV# low going edge)
t
AH(B)
Latency 5
Don’t Ca re
Speed
2
I n f o r m a t i o n
3
Max
S71WS-Nx0 Based MCPs
—
4
t
t
OEL
t
BEL
t
WH
BC
5
t
CD
DQ0
6
Units
ns
DQ1
IH
7
t
OH
).
High -Z
DQ2
8
DQ3
9
t
t
BEADV
WZ
t
HZ
10 11
Symbol
t
AS(B)
t
WES
Valid
t
WL
t
CSS(B)
12 13
Latency 5
t
t
WEH
AH(B)
t
WH
Min
14 15 16 17 18
t
t
BC
BS
D0
Speed
High- Z
D1
t
BH
Max
D2
t
DS
D3
19 20
t
t
DHC
Units
WZ
143
21
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