S71WS256NC0BAWE32 SPANSION [SPANSION], S71WS256NC0BAWE32 Datasheet - Page 143

• Manufacturer Part Number: S71WS256NC0BAWE32
• Description: Stacked Multi-Chip Product (MCP)
• Manufacturer: SPANSION [SPANSION]

September 15, 2005 S71WS-N_01_A4
Latency = 5, Burst Length = 4 (MRS# = V
Notes:
1.
2.
3.
4.
LB#, UB#
Figure 33.3 Asynchronous Write (Address Latch Type) to Synchronous Burst Read Timing
Table 33.3 Asynchronous Write (Address Latch Type) to Burst Read AC Characteristics
WE#
Data in
CLK
ADV#
Address
CS#
OE#
Data out
WAIT#
The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation,
t
/WAIT Low (t
/WAIT High (t
/WAIT High-Z (t
Multiple clock risings are allowed during low ADV# period. The burst operation starts from the first clock rising.
Burst Cycle Time (t
BEADV
Symbol
t
WLRL
should be met.
A d v a n c e
t
AS(A)
WL
WH
Valid
t
WZ
AS
or t
): Data available (driven by Latency-1 clock)
0
): Data don’t care (driven by CS# high going edge)
BC
AWL
Min
) should not be over 2.5µs.
1
t
t
1
CSS(A)
ADV
): Data not available (driven by CS# low going edge or ADV# low going edge)
t
AH(A)
Don’t Ca re
Speed
2
t
WLRL
High- Z
I n f o r m a t i o n
3
Max
S71WS-Nx0 Based MCPs
t
t
t
BW
Read Latency 5
CW
—
AW
4
t
WP
5
High- Z
6
Units
clock
IH
7
Dat a Valid
t
DW
).
8
t
ADVS
t
DH
t
AS(B)
9
Valid
Symbol
10
t
t
WL
AH(B)
t
11
CSS(B)
t
ADVH
T
Latency 5
12 13
Don’t Ca re
Min
14 15 16 17 18
t
t
t
WH
OEL
BEL
t
BC
Speed
t
CD
DQ0
Max
DQ1
t
OH
DQ2
DQ3
19
Units
t
WZ
t
HZ
20
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