LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 20

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

Mobile Intel
3.1.3
3.1.4
3.1.5
3.1.5.1
3.1.5.2
20
®
Celeron
range that the mobile Intel Celeron processor can tolerate. Multiple copies of TMS and TRST#
must be provided, one for each voltage level.
A Debug Port and connector may be placed at the start and end of the JTAG chain containing the
processor, with TDI to the first component coming from the Debug Port and TDO from the last
component going to the Debug Port. There are no requirements for placing the mobile Intel
Celeron processor in the JTAG chain, except for those that are dictated by voltage requirements of
the TAP signals.
Catastrophic Thermal Protection
The mobile Intel Celeron processor does not support catastrophic thermal protection or the
THERMTRIP# signal. An external thermal sensor must be used to protect the processor and the
system against excessive temperatures.
Unused Signals
All signals named NC or RSVD must be unconnected. The TESTHI signal should be pulled up to
V
outputs and bi-directional signals should be unconnected. Unused CMOS active low inputs should
be connected to V
drain outputs should be unconnected. If the processor is configured to enter the Quick Start state
rather than the Stop Grant state, then the SLP# signal should be connected to V
any signal to power or ground, a resistor will allow for system testability. For unused signals, Intel
suggests that 1.5-k resistors are used for pull-ups and 1-k resistors are used for pull-downs.
If the local APIC is hardware disabled, then PICCLK and PICD[1:0] should be tied to V
1-k resistor, one resistor can be used for the three signals. Otherwise PICCLK must be driven
with a clock that meets specification (see Table 18) and the PICD[1:0] signals must be pulled up
to V
BSEL1 must be connected to V
connected to V
If the TAP signals are not used then the inputs should be pulled to ground with 1-k resistors and
TDO should be left unconnected.
Signal State in Low-power States
System Bus Signals
All of the system bus signals have GTL+ input, output, or input/output drivers. Except when
servicing snoops, the system bus signals are tri-stated and pulled up by the termination resistors.
Snoops are not permitted in the Sleep and Deep Sleep states.
CMOS and Open-drain Signals
The CMOS input signals are allowed to be in either the logic high or low state when the processor
is in a low-power state. In the Auto Halt and Stop Grant states these signals are allowed to toggle.
CCT
CCT
. The TESTLO1 and TESTLO2 signal should be pulled down to V
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
with 150- resistors, even if the local APIC is not used.
SS
if they are not used.
CCT
and unused active high inputs should be connected to V
Datasheet
SS
and BSEL0 must be pulled up to V
CCT
SS
. VID[4:0] should be
. Unused GTL+ inputs,
SS
CCT
. Unused Open-
. When tying
283654-003
SS
with a