LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 22

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

Mobile Intel
3.3
3.4
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Figure 4. PLL RLC Filter
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Celeron
System Bus Clock and Processor Clocking
The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The
mobile Intel Celeron processor core frequency is a multiple of the BCLK frequency. The
processor core frequency is configured during manufacturing. The configured bus ratio is visible
to software in the Power-on configuration register, see Section 7.2 for details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for
easier distribution of signals within the system. Clock multiplication within the processor is
provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK
input. During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to
acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in
Section 3.6, AC timing parameters T18 and T47.
Maximum Ratings
Table 8 contains the mobile Intel Celeron processor stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are provided
in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
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Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
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Datasheet
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