LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 43

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LE80538NE0361MES L9LF

Manufacturer Part Number
LE80538NE0361MES L9LF
Description
MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
Manufacturer
Intel
Datasheet
283654-003
Figure 17. High to Low, GTL+ Receiver Ringback Tolerance
Table 25. GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
NOTES:
1. Under no circumstances should the GTL+ signal voltage ever exceed 2.0V maximum with respect to
2. Ringbacks below V
3. Ringbacks above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate
4. System designers are encouraged to follow Intel provided GTL+ layout guidelines.
5. All values are specified by design characterization and are not tested.
V
V
REF,max
REF,min
ground or -2.0V minimum with respect to V
or larger overshoot.
longer or larger undershoot.
Overshoot Amplitude
V
+0.2V
REF,min
-0.2V
Mobile Intel
2.0V
1.9V
1.8V
V
start
CCT
cannot be subtracted from overshoots. Lesser undershoot does not allocate longer
®
2
Celeron
Datasheet
®
Undershoot Amplitude
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
CCT
-0.35V
-0.25V
-0.15V
(i.e., V
CCT
Time
- 2.0V) under operating conditions.
3
V
IL,BCLK
Allowed Pulse Duration
V
IH,BCLK
Clock
0.35 ns
1.2 ns
4.3 ns
1, 4, 5
V0014-02
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