LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 21

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

3.1.5.3
3.2
3.2.1
3.2.2
283654-003
These input buffers have no internal pull-up or pull-down resistors and system logic can use
CMOS or Open-drain drivers to drive them.
The Open-drain output signals have open drain drivers and external pull-up resistors are required.
One of the two output signals (IERR#) is a catastrophic error indicator and is tri-stated (and
pulled-up) when the processor is functioning normally. The FERR# output can be either tri-stated
or driven to V
floating point unit. Since this signal is a DC current path when it is driven to V
recommends that the software clears or masks any floating-point error condition before putting the
processor into the Deep Sleep state.
Other Signals
The system bus clock (BCLK) must be driven in all of the low-power states except the Deep Sleep
state. The APIC clock (PICCLK) must be driven whenever BCLK is driven unless the APIC is
hardware disabled or the processor is in the Sleep state. Otherwise, it is permitted to turn off
PICCLK by holding it at V
Deep Sleep state.
In the Auto Halt and Stop Grant states the APIC bus data signals (PICD[1:0]) may toggle due to
APIC bus messages. These signals are required to be tri-stated and pulled-up when the processor
is in the Quick Start, Sleep, or Deep Sleep states unless the APIC is hardware disabled.
Power Supply Requirements
Decoupling Recommendations
The amount of bulk decoupling required on the V
requirements for the mobile Intel Celeron processor are a strong function of the power supply
design. Contact your Intel Field Sales Representative for tools to help determine how much bulk
decoupling is required. The processor core power plan (V
frequency decoupling capacitors placed underneath the die and twenty 0.1- F mid frequency
decoupling capacitors placed around the die as close to the die as flex solution allows. The system
bus buffer power plane (V
around the die.
Voltage Planes
All V
pins/balls must be connected to the appropriate traces on the system electronics. In addition to the
main V
PLL section. PLL1 and PLL2 should be connected according to Figure 4. Do not connect PLL2
directly to V
CC
CC
and V
, V
CCT
SS
Mobile Intel
SS
. Appendix A contains the RLC filter specification.
SS
, and V
when the processor is in a low-power state depending on the condition of the
pins/balls must be connected to the appropriate voltage plane. All V
SS
power supply signals, PLL1 and PLL2 provide analog decoupling to the
®
CCT
SS
Celeron
. The system bus clock should be held at V
) should have twenty 0.1- F high frequency decoupling capacitors
Datasheet
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
CC
and V
CC
CCT
) should have eight 0.1- F high
planes to meet the voltage tolerance
SS
when it is stopped in the
SS
, Intel
CCT
and V
REF
21