LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 33
LE80538NE0361MES L9LF
Manufacturer Part Number
LE80538NE0361MES L9LF
Description
MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
Manufacturer
Intel
Datasheet
1.LE80538NE0361MES_L9LF.pdf
(80 pages)
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283654-003
Table 21. Stop Grant/Sleep/Deep Sleep AC Specifications
NOTE:
T
±100 mV or 1.60V ±115; V
Symbol
T50
T51
T52
T54
T55
T56
J
= 0°C to 100°C; T
Input signals other than RESET# must be held constant in the Sleep state. The BCLK Settling Time
specification (T60) applies to Deep Sleep state exit under all conditions.
Parameter
SLP# Signal Hold Time from Stop Grant Cycle Completion 100
SLP# Assertion to Input Signals Stable
SLP# Assertion to Clock Stop
SLP# Hold Time from PLL Lock
STPCLK# Hold Time from SLP# Deassertion
Input Signal Hold Time from SLP# Deassertion
Mobile Intel
J
= 5°C to 100°C for Vcc = 1.15V; V
CCT
®
= 1.50V ±115 mV
Celeron
Datasheet
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V
Min Max Unit
10
0
10
10
0
BCLKs Figure 14
ns
BCLKs Figure 14
ns
BCLKs Figure 14
BCLKs Figure 14
Figure
Figure 14
Figure 14
33
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