LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 70

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

Mobile Intel
70
Figure 24. PWRGOOD Relationship at Power On
®
Celeron
specifications. Clean implies that the signal will remain low, (capable of sinking leakage current)
and without glitches, from the time that the power supplies are turned on, until they come within
specification. The signal will then transition monotonically to a high (2.5V) state. Figure 24
illustrates the relationship of PWRGOOD to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable before the rising edge of
PWRGOOD. It must also meet the minimum pulse width specified in Table 16 (Section 3.6) and
be followed by a 1 ms RESET# pulse.
The PWRGOOD signal, which must be supplied to the processor, is used to protect internal
circuits against voltage sequencing issues. The PWRGOOD signal should be driven high
throughout boundary scan operation.
REQ[4:0]# (I/O - GTL+)
The REQ[4:0]# (Request Command) signals must be connected to the appropriate pins/balls on
both agents on the system bus. They are asserted by the current bus owner when it drives A[35:3]#
to define the currently active transaction type.
RESET# (I - GTL+)
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 and L2
caches without writing back Modified (M state) lines. For a power-on type reset, RESET# must
stay active for at least 1 msec after V
specifications and after PWRGOOD has been asserted. When observing active RESET#, all bus
agents will deassert their outputs within two clocks. RESET# is the only GTL+ signal that does
not have on-die GTL+ termination. A 56.2 1% terminating resistor connected to V
required.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for the power-
on configuration. The configuration options are described in Section 7 and in the Pentium
Processor Developer’s Manual.
PWRGOOD
RESET#
®
BCLK
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
V
V
V
CCT
REF
CC
,
,
Datasheet
CC
and BCLK have reached their proper DC and AC
V
IH25,min
1 msec
283654-003
CCT
is
D0026-01
®
II