LE80538NE0361MES L9LF Intel, LE80538NE0361MES L9LF Datasheet - Page 71

• Manufacturer Part Number: LE80538NE0361MES L9LF
• Description: MPU 400 RISC 32-Bit 65nm 1.86GHz 479-Pin BGA
• Manufacturer: Intel

®
®
Mobile Intel
Celeron
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Unless its outputs are tri-stated during power-on configuration, after an active-to-inactive
transition of RESET#, the processor optionally executes its built-in self-test (BIST) and begins
program execution at reset-vector 000FFFF0H or FFFFFFF0H. RESET# must be connected to the
appropriate pins/balls on both agents on the system bus.
RP# (I/O - GTL+)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
RS[2:0]# (I - GTL+)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - GTL+)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent guaranteeing correct parity.
RSVD (TBD)
The RSVD (Reserved) signal is currently unimplemented but is reserved for future use. Leave this
signal unconnected. Intel recommends that a routing channel for this signal be allocated.
RTTIMPEDP (Analog)
The RTTIMPEDP (R
Impedance/PMOS) signal is used to configure the on-die GTL+
TT
termination. Connect the RTTIMPEDP signal to V
with a 56.2- , 1% resistor.
SS
SLP# (I - 1.5V Tolerant)
The SLP# (Sleep) signal, when asserted in the Stop Grant state, causes the processor to enter the
Sleep state. During the Sleep state, the processor stops providing internal clock signals to all units,
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Datasheet
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