M58BW016FB7T3T NUMONYX, M58BW016FB7T3T Datasheet - Page 16

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M58BW016FB7T3T

Manufacturer Part Number
M58BW016FB7T3T
Description
IC FLASH 16MBIT 70NS 80PQFP
Manufacturer
NUMONYX
Datasheet

Specifications of M58BW016FB7T3T

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
16M (512K x 32)
Speed
70ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Package / Case
80-MQFP, 80-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
M58BW016FB7T3TCT
Signal descriptions
2.9
2.10
2.11
2.12
2.13
16/70
Burst Clock (K)
The Burst Clock, K, is used to synchronize the memory with the external bus during
synchronous burst read operations. Bus signals are latched on the active edge of the Clock.
The Clock can be configured to have an active rising or falling edge. In synchronous burst
read mode the address is latched on the first active clock edge when Latch Enable is Low,
V
During asynchronous bus operations the Clock is not used.
Burst Address Advance (B)
The Burst Address Advance, B, controls the advancing of the address by the internal
address counter during synchronous burst read operations.
Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the
X-latency time has expired. If Burst Address Advance is Low, V
counter advances. If Burst Address Advance is High, V
not change; the same data remains on the data inputs/outputs and Burst Address Advance
is not sampled until the Y-latency expires.
The Burst Address Advance, B, may be tied to V
Valid Data Ready (R)
The Valid Data Ready output, R, is an open drain output that can be used, during
synchronous burst read operations, to identify if the memory is ready to output data or not.
The Valid Data Ready output can be configured to be active on the clock edge of the invalid
data read cycle or one cycle before. Valid Data Ready, at V
will be available. When Valid Data Ready is Low, V
active.
In all asynchronous operations, Valid Data Ready is high impedance. It may be tied to other
components with the same Valid Data Ready signal to create a unique system Ready
signal. The Valid Data Ready output has an internal pull-up resistor of around 1 M powered
from V
external timing requirements for Valid Data Ready going to V
Write Protect (WP)
The Write Protect, WP, provides protection against program or erase operations. When
Write Protect, WP, is at V
configuration) parameter blocks and all main blocks are locked. When Write Protect WP is at
V
Supply voltage (V
The supply voltage, V
the V
IL
IH
, or on the rising edge of Latch Enable, whichever occurs first.
all the blocks can be programmed or erased, if no other protection is used.
DD
DDQ
pin, including the program/erase controller.
, designers should use an external pull-up resistor of the correct value to meet the
DD
, is the core power supply. All internal circuits draw their current from
IL
DD
the first two (in the bottom configuration) or last two (in the top
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
)
IL
.
IL
, the previous data outputs remain
IH
, the internal address counter does
IH
IH
, indicates that new data is or
.
IL
, the internal address

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