EPC8QI100 Altera, EPC8QI100 Datasheet

IC CONFIG DEVICE 8MBIT 100-PQFP

EPC8QI100

Manufacturer Part Number
EPC8QI100
Description
IC CONFIG DEVICE 8MBIT 100-PQFP
Manufacturer
Altera
Series
EPCr
Datasheet

Specifications of EPC8QI100

Programmable Type
In System Programmable
Memory Size
8Mb
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1239

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Features
© December 2009 Altera Corporation
CF52002-2.8
This chapter describes the EPC4, EPC8, and EPC16 enhanced configuration devices
(EPC).
Single-chip configuration solution for Altera
APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria
II, FLEX
Stratix II GX devices
Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage
Standard flash die and a controller die combined into single stacked chip package
External flash interface supports parallel programming of flash and external
processor access to unused portions of memory
Page mode support for remote and local reconfiguration with up to eight
configurations for the entire system
Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data
output per DCLK cycle
Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs
Pin-selectable 2-ms or 100-ms power-on reset (POR) time
Configuration clock supports programmable input source and frequency synthesis
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra
FineLine BGA
Supply voltage of 3.3 V (core and I/O)
Hardware compliant with IEEE Std. 1532 in-system programmability (ISP)
specification
On-chip decompression feature almost doubles the effective configuration
density
Flash memory block/sector protection capability via external flash interface
Supported in EPC16 and EPC4 devices
Compatible with Stratix series Remote System Configuration feature
Multiple configuration clock sources supported (internal oscillator and
external clock input pin)
External clock source with frequencies up to 100 MHz
Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of
33, 50, and 66 MHz
Clock synthesis supported via user programmable divide counter
Vertical migration between all devices supported in the 100-pin PQFP package
®
10K (including FLEX 10KE and FLEX 10KA), Mercury
®
(UFBGA) packages
(EPC4, EPC8, and EPC16) Data Sheet
1. Enhanced Configuration Devices
Configuration Handbook (Complete Two-Volume Set)
®
ACEX
®
1K, APEX
®
GX, Cyclone
, Stratix
20K (including
®
, Cyclone
®
II, and

Related parts for EPC8QI100

EPC8QI100 Summary of contents

Page 1

... Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data output per DCLK cycle ■ Supports true n-bit concurrent configuration ( and 8) of Altera FPGAs Pin-selectable 2-ms or 100-ms power-on reset (POR) time ■ ■ Configuration clock supports programmable input source and frequency synthesis Multiple configuration clock sources supported (internal oscillator and ■ ...

Page 2

... The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete ...

Page 3

... Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Functional Description Table 1–2. Configuration Devices Required (Part Family Arria GX Stratix Stratix GX Stratix II Stratix II GX Cyclone © December 2009 Altera Corporation Data Size (Bits) Device (1) EPC4 EP1AGX20C 9,640,672 EP1AGX35C 9,640,672 EP1AGX35D ...

Page 4

... EP2A15 4,358,512 EP2A25 6,275,200 EP2A40 9,640,528 EP2A70 17,417,088 EPF10K10 118,000 EPF10K20 231,000 EPF10K30 376,000 EPF10K40 498,000 EPF10K50 621,000 EPF10K70 892,000 EPF10K100 1,200,000 Functional Description (2) EPC8 (2) EPC16 ( — — — — — — — — — © December 2009 Altera Corporation ...

Page 5

... Memory-Based EPC4, EPC8 and EPC16 Devices EPC devices support three different types of flash memory. supported flash memory for all EPC devices. Table 1–3. Enhanced Configuration Devices Flash Memory (Part Device EPC4 EPC8 © December 2009 Altera Corporation Data Size (Bits) Device (1) EPF10K10A 120,000 EPF10K30A ...

Page 6

... Source for EPC4, EPC8 and EPC16 Enhanced Configuration The external flash interface is currently supported in the EPC16 and EPC4 devices. For information about using this feature in the EPC8 device, contact Altera Applica- tions at www.altera.com/support. Enhanced configuration devices have a 3.3-V core and I/O interface. The controller chip is a synchronous system that implements the various interfaces and features. Figure 1– ...

Page 7

... DCLK and DATA[] output pins. The controller selects the configuration page to be transmitted to the FPGA by sampling its PGM[2..0] pins after POR or reset. © December 2009 Altera Corporation Remote chapter in the Stratix Device Configuration Handbook (Complete Two-Volume Set) ...

Page 8

... MHz). Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported by Altera FPGAs are much higher and translate to high configuration write bandwidths. For instance, 100-MHz Stratix FPP configuration requires data at the rate of 800 Mbps (8-bit DATA[] bus at 100 MHz) ...

Page 9

... Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Functional Description Configuration Signals Table 1–4 lists the configuration signal connections between the enhanced configuration device and Altera FPGAs. Table 1–4. Configuration Signals Enhanced Configuration Device Pin DATA[] DCLK nINIT_CONF, which ...

Page 10

... While Altera FPGAs can be cascaded in a configuration chain, the enhanced configuration devices cannot be cascaded to configure larger devices or chains. Configuration Handbook (Complete Two-Volume Set) Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet ...

Page 11

... PS mode using an enhanced configuration device. f For specific details about configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the appropriate FPGA family chapter in the © December 2009 Altera Corporation Configuration Handbook. Configuration Handbook (Complete Two-Volume Set) 1–11 ...

Page 12

... TM0 to GND, and WP supply from V . For more information, refer section CCW CC Functional Description Device WE#F RP#F N.C. A[20..0] N.C. RY/BY# N.C. CE# N.C. OE# N.C. DQ[15..0] (3) V (7) CC VCCW (4) PORSEL (4) PGM[2..0] EXCLK (4) A0-F A1-F A15-F A16-F “Intel-Flash-Based EPC © December 2009 Altera Corporation ...

Page 13

... Since the internal flash interface is directly connected to the external flash interface pins, controller flash access cycles will toggle the external flash interface pins. The external device must be able to tri-state its flash interface during these operations and ignore transitions on the flash interface pins. © December 2009 Altera Corporation Mode (n =) (1) Used Outputs ...

Page 14

... For the Intel Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Datasheet, visit www.intel.com. Configuration Handbook (Complete Two-Volume Set) Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Altera Enhanced Configuration Devices Functional Description chapter in volume 2 of the © December 2009 Altera Corporation ...

Page 15

... Figure 1–4: (1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications. (2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins should not be connected to any signal; they are no-connect pins. ...

Page 16

... < V until V is fully powered up. PP PPLK powered up. PP < PPLK . CC should reach the minimum V CC Functional Description disables writes. PPLK is a programming PP is equivalent to the VCCW pin on PP before 50 ms and RP# CC © December 2009 Altera Corporation ...

Page 17

... For detailed information about the page-mode feature implementation and programming file generation steps using the Quartus II software, refer to the Enhanced Configuration Devices © December 2009 Altera Corporation in the Stratix Device Handbook. chapter in volume 2 of the Configuration Handbook. Configuration Handbook (Complete Two-Volume Set) 1– ...

Page 18

... These unused routing and logic resources as well as un-initialized memory structures result in a large number of configuration RAM bits in the disabled state. Altera's proprietary compression algorithm takes advantage of such bitstream qualities. The general guideline for effectiveness of compression is the higher the device ...

Page 19

... External Clock (Up to 100 MHz) The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports. f The maximum DCLK input frequency supported by the FGPA is specified in the appropriate FPGA family chapter in the © December 2009 Altera Corporation (Note 1) Minimum 98% 1.9 47% Figure 1–5 ...

Page 20

... Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet Table 1–7. Min (MHz) Typ (MHz) 6.4 8.0 21.0 26.5 32.0 40.0 42.0 53.0 Altera Enhanced Configuration Devices © December 2009 Altera Corporation Functional Description Max (MHz) 10.0 33.0 50.0 66.0 chapter in volume 2 ...

Page 21

... Pin Name Pin Type Output DATA[7..0] Output DCLK © December 2009 Altera Corporation Table 1–10 describe the enhanced configuration device pins. These Description Configuration data output bus. DATA changes on each falling edge of DCLK. DATA is latched into the FPGA on the rising edge of DCLK. ...

Page 22

... Active low flash input pin that activates the flash memory when asserted. When it is high, it deselects the device and reduces power consumption to standby levels. This flash input pin is internally connected to the controller. Leave this pin floating on the board when the external flash interface is not used. Pin Description © December 2009 Altera Corporation ...

Page 23

... Supply CCW Open-Drain Output RY/BY# © December 2009 Altera Corporation Description Active low flash input pin that resets the flash when asserted. When high, it enables normal operation. When low, it inhibits write operation to the flash memory, which provides data protection during power transitions. ...

Page 24

... This pin must be connected to a valid logic level. For normal operation, this test pin must be connected to GND. For normal operating, this test pin must be connected to V Pin Description of the Intel flash die CCQ without using any CC white paper © December 2009 Altera Corporation ...

Page 25

... FPGA detects a CRC error or if the FPGA’s nCONFIG input pin is asserted ■ The controller detects a configuration error and asserts OE to begin re-configuration of the Altera FPGA (for example, when CONF_DONE stays low after all configuration data has been transmitted) Power Sequencing Altera requires that you power-up the FPGA's V configuration device's POR expires ...

Page 26

... Selects the USERCODE register and places it between TDI and TDO, allowing the USERCODE to be serially shifted out the TDO. The 32-bit USERCODE is a programmable user-defined pattern. Programming and Configuration File Support Altera Enhanced section in volume 2 of the © December 2009 Altera Corporation ...

Page 27

... Intel HEX format file (.hexout) using the Quartus II Convert Programming Files utility, for use with the programmers or processors. You can also program the enhanced configuration devices using the Quartus II software, the Altera Programming Unit (APU), and the appropriate configuration device programming adapter. with each enhanced configuration device. ...

Page 28

... JPSU JPH t t JPZX JPCO t t JSSU JSH t t JSZX JSCO JSXZ Parameter IEEE Std. 1149.1 (JTAG) Boundary-Scan t JPXZ Min Max Unit 100 — — — — — ns — — — — — ns — — — © December 2009 Altera Corporation ...

Page 29

... For more information about the flash memory (external flash interface) timing, refer to the appropriate flash data sheet on the Altera website at www.altera.com. ■ For Micron flash-based EPC4, refer to the Micron MT28F400B3 Data Sheet Flash Memory Used in EPC4 Devices at For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory ■ ...

Page 30

... Min Max Unit -0.2 4.6 V -0.5 3.6 V — 100 mA - — 360 mW -65 150 C -65 135 C — 135 C Min Max Unit 3.0 3.6 V –0 0 – — — © December 2009 Altera Corporation ...

Page 31

... I V supply current CCW CCW Note to Table 1–18: (1) For V supply current information, refer to the appropriate flash memory data sheet at www.altera.com. CCW Table 1–19. Enhanced Configuration Device Capacitance Symbol Parameter CIN Input pin capacitance COUT Output pin capacitance Package The EPC16 enhanced configuration device is available in both the 88-pin UFBGA package and the 100-pin PQFP package ...

Page 32

... Pin pin for Intel Flash-based EPC16. Package Layout Recommendation Sharp flash-based EPC16 and EPC8 enhanced configuration devices in the 100-pin PQFP packages have different package dimensions than other Altera 100-pin PQFP devices (including the Micron flash-based EPC4, Intel flash-based EPC16, EPC8 and EPC4). ...

Page 33

... Used 0.3-mm increase to maximum foot width. f For package outline drawings, refer to the Device Pin-Outs f For pin-out information, refer to © December 2009 Altera Corporation 0.65-mm Pad Pitch 0.410 mm 25.3 mm Altera Device Package Information Data Altera Configuration Devices Pin-Out Configuration Handbook (Complete Two-Volume Set) 1– ...

Page 34

... Updated VCCW connection in Figure 2–2, Figure 2–3, and Figure 2–4. Updated (Note 2) of Figure 2–2, Figure 2–3, and Figure 2–4. Updated (Note 4) of Table 2–12. Updated unit of ICC0 in Table 2–16. Added ICCW to Table 2–16. Initial Release. Chapter Revision History © December 2009 Altera Corporation ...

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