EPC8QI100 Altera, EPC8QI100 Datasheet - Page 26

• Manufacturer Part Number: EPC8QI100
• Description: IC CONFIG DEVICE 8MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC8QI100

• Programmable Type: In System Programmable
• Memory Size: 8Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1239

1–26
Programming and Configuration File Support
Table 1–11. Enhanced Configuration Device JTAG Instructions (Part 1 of 2)
Configuration Handbook (Complete Two-Volume Set)
SAMPLE/
PRELOAD
EXTEST
BYPASS
IDCODE
USERCODE
JTAG Instruction
f
00 0101 0101
00 0000 0000
11 1111 1111
00 0101 1001
00 0111 1001
Alternatively, a power-monitoring circuit or a power-good signal can be used to keep
the FPGA’s nCONFIG pin asserted low until both supplies have stabilized. This
ensures the correct power up sequence for successful configuration.
The Quartus II software provides programming support for the enhanced
configuration device and automatically generates the .pof for the EPC4, EPC8, and
EPC16 devices. In a multi-device project, the software can combine the .sof for
multiple ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and
Stratix series FPGAs into one programming file for the enhanced configuration
device.
For details about generating programming files, refer to the
Configuration Devices
Configuration Handbook.
Enhanced configuration devices can be programmed in-system through the
industry-standard 4-pin JTAG interface. The ISP feature in the enhanced
configuration device provides ease in prototyping and updating FPGA functionality.
After programming an enhanced configuration device in-system, FPGA configuration
can be initiated by including the enhanced configuration device’s JTAG INIT_CONF
instruction
The ISP circuitry in the enhanced configuration device is compliant with the IEEE Std.
1532 specification. The IEEE Std. 1532 is a standard that allows concurrent ISP
between devices from multiple vendors.
OPCODE
(Table
Allows a snapshot of the state of the enhanced configuration device pins to be
captured and examined during normal device operation and permits an initial
data pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by
forcing a test pattern at the output pins and capturing results at the input pins.
Places the 1-bit bypass register between the TDI and the TDO pins, which allow
the BST data to pass synchronously through a selected device to adjacent
devices during normal device operation.
Selects the device IDCODE register and places it between TDI and TDO,
allowing the device IDCODE to be serially shifted out to TDO. The device
IDCODE for all enhanced configuration devices is the same and shown below:
0100A0DDh
Selects the USERCODE register and places it between TDI and TDO, allowing
the USERCODE to be serially shifted out the TDO. The 32-bit USERCODE is a
programmable user-defined pattern.
1–11).
chapter and the
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Software Settings
(Note 1)
Description
Programming and Configuration File Support
section in volume 2 of the
© December 2009 Altera Corporation
Altera Enhanced