EPC8QI100 Altera, EPC8QI100 Datasheet - Page 12

• Manufacturer Part Number: EPC8QI100
• Description: IC CONFIG DEVICE 8MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC8QI100

• Programmable Type: In System Programmable
• Memory Size: 8Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1239

1–12
Figure 1–3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
Notes to
(1) Connect V
(2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is always active. This means an
(3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external
(4) For PORSEL, PGM[], and EXCLK pin connections, refer to
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to
(6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the
(7) To protect Intel Flash based EPC devices content, isolate the V
Configuration Handbook (Complete Two-Volume Set)
external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its
functionality is not used. If nINIT_CONF is not used, nCONFIG must be pulled to V
pull-up resistors should not be used on these pins. The internal pull-up resistors are used by default in the Quartus II software. To turn off the
internal pull-up resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
F-A16, and BYTE# to V
C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V
Configuration
Device Protection” on page
Figure
CC
1–3:
to the same supply voltage as the configuration device.
(6)
Handbook.
(6)
(6)
N.C.
N.C.
N.C.
n
n
n
CC
. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages:
1–15.
MSEL
nCEO
MSEL
nCEO
MSEL
nCEO
FPGA1
FPGA7
FPGA0
CONF_DONE
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCONFIG
nSTATUS
nSTATUS
nSTATUS
DATA0
DATA0
DATA0
DCLK
DCLK
DCLK
nCE
nCE
nCE
CC
, TM0 to GND, and WP# to V
GND
GND
GND
V
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
CC
Table
(3)
CCW
(1)
supply from V
1–10.
V
CC
(3)
(1)
CC
GND
CC
V
.
(1)
CC
. For more information, refer section
Enhanced Configuration
BYTE# (5)
WP#
TM1
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
WE#C
RP#C
DCLK
DATA0
DATA1
OE
nCS
nINIT_CONF (2)
DATA 7
TMO
CC
either directly or through a resistor.
(3)
(3)
Device
PGM[2..0]
DQ[15..0]
PORSEL
A[20..0]
RY/BY#
EXCLK
VCCW
WE#F
A0-F
A1-F
A15-F
A16-F
RP#F
OE#
CE#
© December 2009 Altera Corporation
V
CC
(4)
(4)
(4)
(7)
“Intel-Flash-Based EPC
Functional Description
N.C.
N.C.
N.C.
N.C.
N.C.