SE98ATP,547 NXP Semiconductors, SE98ATP,547 Datasheet - Page 33

• Manufacturer Part Number: SE98ATP,547
• Description: IC TEMP SENSOR DDR 8-HWSON
• Manufacturer: NXP Semiconductors

Specifications of SE98ATP,547

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 1.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-WSON (Exposed Pad), 8-HWSON
• Temperature Threshold: Programmable
• Full Temp Accuracy: +/- 1 C
• Digital Output - Bus Interface: 2-Wire, SMBus, I2C
• Digital Output - Number Of Bits: 11
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.7 V
• Description/function: DDR Memory Module Temperature Sensor
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 250 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4731-2; SE98ATP,147

NXP Semiconductors
Table 27.
V
The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I
to 400 kHz.
[1]
[2]
[3]
[4]
[5]
[6]
SE98A_4
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
HIGH
LOW
to(SMBus)
r
f
SU;DAT
h(i)(D)
HD;DAT
SU;STA
HD;STA
SU;STO
BUF
SP
VD;DAT
f(o)
POR
DD
Minimum clock frequency is 0 kHz if SMBus Time-out is disabled.
A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the V
undefined region of the falling edge of SCL.
Delay from SCL HIGH-to-LOW transition to SDA edges.
Delay from SCL LOW-to-HIGH transition to restart SDA.
Delay from SDA START to first SCL HIGH-to-LOW transition.
= 1.7 V to 3.6 V; T
Delay from SDA STOP to SDA START.
Parameter
SCL clock frequency
HIGH period of the SCL clock 70 % to 70 %
LOW period of the SCL clock 30 % to 30 %
SMBus time-out time
rise time of both SDA and
SCL signals
fall time of both SDA and SCL
signals
data set-up time
data input hold time
data hold time
set-up time for a repeated
START condition
hold time (repeated) START
condition
set-up time for STOP
condition
bus free time between a
STOP and START condition
pulse width of spikes that
must be suppressed by the
input filter
data valid time
output fall time
power-on reset pulse time
SMBus AC characteristics
amb
=
−
40
°
C to +125
Conditions
LOW period to reset
SMBus
30 % of SDA to
70 % of SCL
from clock
power supply falling
°
C; unless otherwise specified. These specifications are guaranteed by design.
Rev. 04 — 25 November 2009
DDR memory module temp sensor, 1.7 V to 3.6 V
[2][3]
[4]
[5]
[6]
[2]
Standard mode
4000
4700
4700
4000
4000
4700
10
Min
250
200
200
0.5
25
0
-
-
-
-
[1]
1000
3450
Max
100
300
35
50
-
-
-
-
-
-
-
-
-
-
-
IH(min)
of the SCL signal) to bridge the
1300
1300
10
Min
200
600
100
200
600
600
600
0.5
Fast mode
25
20
0
-
-
-
[1]
© NXP B.V. 2009. All rights reserved.
2
SE98A
C-bus from DC
Max
300
300
900
250
400
35
50
-
-
-
-
-
-
-
-
-
-
33 of 43
Unit
kHz
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs