EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 16
![KIT DEV FOR ADUC832 QUICK START](/photos/9/24/92469/eval-aduc832qs_sml.jpg)
EVAL-ADUC832QSZ
Manufacturer Part Number
EVAL-ADUC832QSZ
Description
KIT DEV FOR ADUC832 QUICK START
Manufacturer
Analog Devices Inc
Series
QuickStart™ Kitr
Type
MCUr
Specifications of EVAL-ADUC832QSZ
Contents
Evaluation Board, Cable, Power Supply, Software and Documentation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADuC832
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
EVAL-ADUC832QS
EVAL-ADUC832QS
EVAL-ADUC832QS
- Current page: 16 of 92
- Download datasheet (2Mb)
ADuC832
Table 8. SPI Master Mode Timing (CPHA = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
See Figure 10.
Characterized under the following conditions:
a. Core clock divider bits (CD2, CD1, and CD0 bits in PLLCON SFR) set to 0, 1, and 1, respectively, that is, core clock frequency = 2.09 MHz
b. SPI bit rate selection bits (SPR1 and SPR0 bits in SPICON SFR) set to 0 and 0, respectively.
1
SCLOCK (O)
SCLOCK (O)
(CPOL = 0)
(CPOL = 1)
MOSI (O)
MISO (I)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
t
DAV
t
SH
2
2
t
DSU
Figure 10. SPI Master Mode Timing (CPHA = 1)
MSB IN
t
DHD
MSB
t
SL
Rev. A | Page 16 of 92
t
DF
t
DR
BIT 6 TO 1
BIT 6 TO 1
t
SR
Min
100
100
t
LSB IN
SF
LSB
Typ
476
476
10
10
10
10
Max
50
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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