EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 41

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

CONFIGURING THE ADC
The ADuC832’s successive approximation ADC is driven by a
divided down version of the master clock. To ensure adequate
ADC operation, this ADC clock must be between 400 kHz and
6 MHz, and optimum performance is obtained with ADC clock
between 400 kHz and 4.5 MHz. Frequencies within this range
can easily be achieved with master clock frequencies from 400 kHz
to well above 16 MHz with the four ADC clock divide ratios to
choose from. For example, set the ADC clock divide ratio to 4
(that is, ADCCLK = 16.78 MHz/8 = 2 MHz) by setting the
appropriate bits in ADCCON1 (ADCCON1[5:4] = 00).
The total ADC conversion time is 15 ADC clocks, plus 1 ADC
clock for synchronization, plus the selected acquisition time
(one, two, three, or four ADC clocks). For the preceding example,
with a three-clock acquisition time, total conversion time is
19 ADC clocks (or 9.05 sec for a 2 MHz ADC clock).
In continuous conversion mode, a new conversion begins each
time the previous one finishes. The sample rate is then simply
the inverse of the total conversion time previously described. In
the preceding example, the continuous conversion mode sample
rate would be 110.3 kHz.
If using the temperature sensor as the ADC input, the ADC
should be configured to use an ADCCLK of MCLK/32 and four
acquisition clocks.
Increasing the conversion time on the temperature sensor channel
improves the accuracy of the reading. To further improve the
accuracy, an external reference with low temperature drift
should also be used.
ADC DMA MODE
The on-chip ADC is designed to run at a maximum conversion
speed of 4 μs (247 kSPS sampling rate). When converting at this
rate, the ADuC832 MicroConverter® has 4 μs to read the ADC
result and store the result in memory for further postprocessing;
otherwise, the next ADC sample may be lost. In an interrupt
driven routine, the MicroConverter also has to jump to the ADC
interrupt service routine, which also increases the time required
to store the ADC results. In applications where the ADuC832
REFERENCE
EXTERNAL
VOLTAGE
V
DD
Figure 43. Using an External Voltage Reference
V
0.1µF
C
0.1µF
REF
REF
8
7
51Ω
BUFFER
REFERENCE
BAND GAP
ADuC832
2.5V
Rev. A | Page 41 of 92
cannot sustain the interrupt rate, an ADC DMA mode is
provided.
To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set.
This allows the ADC results to be written directly to a 16 MB
external static memory SRAM (mapped into data memory
space) without any interaction from the ADuC832 core. This
mode allows the ADuC832 to capture a contiguous sample
stream at full ADC update rates (247 kSPS).
A Typical DMA Mode Configuration Example
To set the ADuC832 into DMA mode, a number of steps must
be followed:
1.
2.
3.
4.
00000AH
000000H
The ADC must be powered down. This is done by ensuring
MD1 is set to 0 in ADCCON1.
The DMA address pointer must be set to the start address
of where the ADC results are to be written. This is done by
writing to the DMA mode address pointers DMAL, DMAH,
and DMAP. DMAL must be written to first, followed by
DMAH, and then by DMAP.
The external memory must be preconfigured. This consists
of writing the required ADC channel IDs into the top four
bits of every second memory location in the external SRAM,
starting at the first address specified by the DMA address
pointer. Because the ADC DMA mode operates indepen-
dent from the ADuC832 core, it is necessary to provide it
with a stop command. This is done by duplicating the last
channel ID to be converted, followed by 1111 into the next
channel selection field. A typical preconfiguration of
external memory is as follows:
Initiate the DMA by writing to the ADC SFRs in the
following sequence:
a.
b.
c.
Figure 44. Typical DMA External Memory Preconfiguration
1
1
0
0
0
0
ADCCON2 is written to enable the DMA mode, that
is, MOV ADCCON2, #40H; DMA mode enabled.
ADCCON1 is written to configure the conversion
time and power-up of the ADC. It can also enable
Timer 2 driven conversions or external triggered
conversions if required.
ADC conversions are initiated. This is done by
starting single conversions, starting Timer 2, running
for Timer 2 conversions, or receiving an external
trigger.
1
1
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
STOP COMMAND
REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION
CONVERT ADC CH 3
CONVERT TEMP SENSOR
CONVERT ADC CH 5
CONVERT ADC CH 2
ADuC832