EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 33

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

SPECIAL FUNCTION REGISTERS (SFRS)
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addressing only.
It provides an interface between the CPU and all on-chip peripher-
als. A block diagram showing the programming model of the
ADuC832 via the SFR area is shown in Figure 35.
All registers, except the program counter (PC) and the four
general-purpose register banks, reside in the SFR area. The SFR
registers include control, configuration, and data registers that
provide an interface between the CPU and all on-chip peripherals.
ACCUMULATOR SFR (ACC)
ACC is the accumulator register and is used for math operations
including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.
B SFR (B)
The B register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated
as a general-purpose scratch pad register.
STACK POINTER (SP AND SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the top of the stack. The SP register
is incremented before data is stored during push and call
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at Location 08H.
As mentioned previously, the ADuC832 offers an extended
11-bit stack pointer. The three extra bits to make up the 11-bit
stack pointer are the three LSBs of the SPH byte located at B7H.
DATA POINTER (DPTR)
The data pointer is made up of three 8-bit registers, named DPP
(page byte), DPH (high byte), and DPL (low byte). These are
FLASH/EE PROGRAM
REPROGRAMMABLE
ELECTRICALLY
COMPATIBLE
NONVOLATILE
2304 BYTES
MEMORY
CORE
8051-
RAM
62-kB
Figure 35. Programming Model
FUNCTION
REGISTER
128-BYTE
SPECIAL
AREA
REPROGRAMMABLE
FLASH/EE DATA
OTHER ON-CHIP
2
ELECTRICALLY
TEMPERATURE
NONVOLATILE
PERIPHERALS
8-CHANNEL
12-BIT ADC
SERIAL I/O
MEMORY
SENSOR
12-BIT DACs
PWM
4-kB
WDT
PSM
TIC
Rev. A | Page 33 of 92
used to provide memory addresses for internal and external
code access and external data access. It can be manipulated as a
16-bit register (DPTR = DPH, DPL), although INC DPTR
instructions automatically carry over to DPP, or as three
independent 8-bit registers (DPP, DPH, and DPL).
The ADuC832 supports dual data pointers. Refer to the Dual
Data Pointers section.
PROGRAM STATUS WORD (PSW)
SFR Address:
Power-On Default Value:
Bit Addressable:
The PSW SFR contains several bits reflecting the current status
of the CPU, as detailed in Table 14.
Table 14. PSW SFR Bit Designations
Bit
[7]
[6]
[5]
[4:3]
[2]
[1]
[0]
POWER CONTROL SFR (PCON)
SFR Address:
Power-On Default Value:
Bit Addressable:
The PCON SFR contains bits for power-saving options and
general-purpose status flags, as shown in Table 15.
Table 15. PCON SFR Bit Designations
Bit
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Name
SMOD
SERIPD
INT0PD
ALEOFF
GF1
GF0
PD
IDL
Name
CY
AC
F0
RS[1:0]
OV
F1
P
Description
Carry flag
Auxiliary carry flag
General-purpose flag
Register bank select bits
RS1
0
0
1
1
Overflow flag
General-purpose flag
Parity bit
Description
Double UART baud rate
I
INT0 power-down interrupt enable
Disable ALE output
General-purpose flag bit
General-purpose flag bit
Power-down mode enable
Idle mode enable
2
C/SPI power-down interrupt enable
D0H
00H
Yes
87H
00H
No
RS0
0
1
0
1
Selected Bank
0
1
2
3
ADuC832