EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 37

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADCCON2 (ADC Control SFR 2)
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
Table 17. ADCCON2 SFR Bit Designations
Bit
[7]
[6]
[5]
[4]
[3:0]
Name
ADCI
DMA
CCONV
SCONV
CS[3:0]
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block
conversion. ADCI is cleared by hardware when the PC vectors to the ADC interrupt service routine. Otherwise, the ADCI bit
should be cleared by user code.
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode of operation. A more
detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is automatically cleared to 0 at the
end of a DMA cycle. Setting this bit causes the ALE output to cease, starting again when DMA is started, and operates
correctly after DMA is complete.
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of conversion. In this
mode, the ADC starts converting based on the timing and channel configuration already set up in the ADCCONx SFRs; the
ADC automatically starts another conversion once a previous conversion has completed.
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is automatically reset to 0 on
completion of the single conversion cycle.
The channel selection bits (CS[3:0] allow the user to program the ADC channel selection under software control. When a
conversion is initiated, the channel converted is the one selected by these channel selection bits. In DMA mode, the
channel selection is derived from the channel ID written to the external memory.
CS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
All other combinations reserved
Description
CS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
D8H
00H
Yes
CS1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
CS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Channel Number
0
1
2
3
4
5
6
7
Temperature sensor (requires minimum of 1 μs to acquire)
DAC0 (only use with internal DAC output buffer on)
DAC1 (only use with internal DAC output buffer on)
AGND
V
DMA stop (place in XRAM location to finish DMA sequence, see the ADC DMA
Mode section)
Rev. A | Page 37 of 92
REF
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed in Table 17.
ADuC832