MC9S08SH4CTJ Freescale Semiconductor, MC9S08SH4CTJ Datasheet - Page 65

IC MCU 8BIT 4K FLASH 20-TSSOP

MC9S08SH4CTJ

Manufacturer Part Number
MC9S08SH4CTJ
Description
IC MCU 8BIT 4K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08SH4CTJ

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
A/d Bit Size
10 bit
A/d Channels Available
12
Height
1.05 mm
Length
6.6 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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5.6
The MC9S08SH8 includes a system to protect against low voltage conditions in order to protect memory
contents and control MCU system states during supply voltage variations. The system is comprised of a
power-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVD
circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon entering any of the stop
modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter
stop2, and the current consumption in stop3 with the LVD enabled will be higher.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
LVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection low
threshold, V
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset has
occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.6.3
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching the low voltage condition. When a low voltage warning condition is detected and is
configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt
request will occur.
5.7
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of
Freescale Semiconductor
Table 4-2
Low-Voltage Detect (LVD) System
Reset, Interrupt, and System Control Registers and Control Bits
Power-On Reset Operation
Low-Voltage Detection (LVD) Reset Operation
Low-Voltage Warning (LVW) Interrupt Operation
LVDL
. Both the POR bit and the LVD bit in SRS are set following a POR.
and
POR
Operation.”
Table 4-3
, the POR circuit will cause a reset condition. As the supply voltage rises, the
in
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Chapter 4,
“Memory,” of this data sheet for the absolute address
Chapter 5 Resets, Interrupts, and General System Control
65

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