MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 102

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output Control
6.5.4.3
6.5.4.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
102
PTDPE[7:0]
PTDSE[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
rate control to the desired value to ensure correct operation.
W
W
R
R
PTDPE7
PTDSE7
Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port D bit n.
1 Internal pull-up/pull-down device enabled for port D bit n.
Output Slew Rate Enable for Port D Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
Port D Pull Enable Register (PTDPE)
0
Port D Slew Rate Enable Register (PTDSE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
PTDPE6
PTDSE6
Figure 6-26. Internal Pull Enable for Port D Register (PTDPE)
Figure 6-27. Slew Rate Enable for Port D Register (PTDSE)
0
0
6
6
Table 6-24. PTDPE Register Field Descriptions
Table 6-25. PTDSE Register Field Descriptions
PTDPE5
PTDSE5
MC9S08DZ60 Series Data Sheet, Rev. 4
0
0
5
5
PTDPE4
PTDSE4
NOTE
0
0
4
4
Description
Description
PTDPE3
PTDSE3
3
0
3
0
PTDPE2
PTDSE2
0
0
2
2
PTDPE1
PTDSE1
Freescale Semiconductor
0
0
1
1
PTDPE0
PTDSE0
0
0
0
0