MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 222

• Manufacturer Part Number: MC9S08DZ60ACLF
• Description: IC MCU 60K FLASH 4K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ60ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• For Use With: DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
12.1.3
12.2
The MSCAN uses two external pins:
12.2.1
RXCAN is the MSCAN receiver input pin.
12.2.2
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
12.2.3
A typical CAN system with MSCAN is shown in
the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective nodes.
222
Wake-Up Interrupt Req.
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Oscillator Clock
External Signal Description
0 = Dominant state
1 = Recessive state
Block Diagram
RXCAN — CAN Receiver Input Pin
TXCAN — CAN Transmitter Output Pin
CAN System
Bus Clock
MSCAN
Figure 12-2. MSCAN Block Diagram
MUX
MC9S08DZ60 Series Data Sheet, Rev. 4
Configuration
CANCLK
Registers
Control
Status
and
Figure
Presc.
12-3. Each CAN node is connected physically to
Tq Clk
Wake-Up
Low Pass Filter
Message
Buffering
Receive/
Transmit
Filtering
Engine
and
Freescale Semiconductor
RXCAN
TXCAN