MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 172

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

External Interrupt Module (IRQ)
The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge
and low-level triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of the following occur:
The vector fetch or software clear may occur before or after the interrupt pin returns to a high level. As
long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt requests. A latched interrupt request is
not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
172
$001A
Addr.
•
•
Vector fetch or software clear
Return of the interrupt pin to a high level
IRQ
IRQ Status/Control Register (ISCR)
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See
DECODER
VECTOR
FETCH
Register Name
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
ACK
Figure 17-2. IRQ I/O Register Summary
V
MODE
DD
Figure 17-1. IRQ Block Diagram
D
Read:
CK
Write:
LATCH
CLR
IRQ
Q
Bit 7
R
R
0
NOTE
= Reserved
R
6
0
IMASK
R
5
0
SYNCHRO-
VOLTAGE
DETECT
NIZER
HIGH
R
4
0
IRQF
R
3
Figure
IRQF
ACK
Freescale Semiconductor
17-3).
2
0
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
IMASK
1
MODE
Bit 0