MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 216

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

Serial Peripheral Interface (SPI)
19.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests:
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt,
provided that the SPI is enabled (SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a
receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
flag is enabled to generate receiver/error CPU interrupt requests.
Two sources in the SPI status and control register can generate CPU interrupt requests:
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1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
SPTE (Transmitter Empty)
SPRF (Receiver Full)
OVRF (Overflow)
MODF (Mode Fault)
ERRIE
MODF
OVRF
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Flag
Figure 19-9. SPI Interrupt Request Generation
SPRIE
SPTE
Table 19-3. SPI Interrupts
SPTIE
SPRF
SPI Transmitter CPU Interrupt Request (SPTIE = 1)
SPI Receiver CPU Interrupt Request (SPRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1)
SPI Receiver/Error Interrupt Request
(SPRIE = 1, ERRIE = 1, MODFEN = 1)
SPE
Request
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
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