MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 283

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

Freescale Semiconductor
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
$05b
Addr
Addr
C
0
1
2
3
4
5
6
7
8
9
A
B
0
1
2
3
Register
Register
Figure 23-11. Receive/Transmit Message Buffer Extended Identifier (IDRn)
IDR0
IDR1
IDR2
IDR3
DSR0
DSR1
DSR2
DSR3
DSR4
DSR5
DSR6
DSR7
IDR0
IDR1
IDR2
IDR3
DLR
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 23-12. Standard Identifier Mapping
Bit 7
ID10
ID2
Bit 7
ID28
ID20
ID14
DB7
DB7
DB7
DB7
DB7
DB7
DB7
DB7
ID6
= Unimplemented
= Unimplemented
ID9
ID1
6
ID27
ID19
ID13
DB6
DB6
DB6
DB6
DB6
DB6
DB6
DB6
ID5
6
ID8
ID0
5
ID26
ID18
ID12
DB5
DB5
DB5
DB5
DB5
DB5
DB5
DB5
ID4
5
SRR (=1)
RTR
ID7
4
ID25
ID11
DB4
DB4
DB4
DB4
DB4
DB4
DB4
DB4
ID3
4
Programmer’s Model of Message Storage
IDE(=0)
IDE (=1)
ID6
DLC3
ID24
ID10
3
DB3
DB3
DB3
DB3
DB3
DB3
DB3
DB3
ID2
3
DLC2
ID5
ID23
ID17
DB2
DB2
DB2
DB2
DB2
DB2
DB2
DB2
ID9
ID1
2
2
DLC1
ID4
ID22
ID16
DB1
DB1
DB1
DB1
DB1
DB1
DB1
DB1
ID8
ID0
1
1
DLC0
Bit 0
Bit 0
ID21
ID15
RTR
DB0
DB0
DB0
DB0
DB0
DB0
DB0
DB0
ID3
ID7
283