MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 246

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

Programmable Interrupt Timer (PIT)
POF — PIT Overflow Flag Bit
POIE — PIT Overflow Interrupt Enable Bit
PSTOP — PIT Stop Bit
PRST — PIT Reset Bit
PPS[2:0] — Prescaler Select Bits
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This read/write flag is set when the PIT counter reaches the modulo value programmed in the PIT
counter modulo registers. Clear POF by reading the PIT status and control register when POF is set
and then writing a 0 to POF. If another PIT overflow occurs before the clearing sequence is complete,
then writing 0 to POF has no effect. Therefore, a POF interrupt request cannot be lost due to
inadvertent clearing of POF. Reset clears the POF bit. Writing a 1 to POF has no effect.
This read/write bit enables PIT overflow interrupts when the POF bit becomes set. Reset clears the
POIE bit.
This read/write bit stops the PIT counter. Counting resumes when PSTOP is cleared. Reset sets the
PSTOP bit, stopping the PIT counter until software clears the PSTOP bit.
Setting this write-only bit resets the PIT counter and the PIT prescaler. Setting PRST has no effect on
any other registers. Counting resumes from $0000. PRST is cleared automatically after the PIT
counter is reset and always reads as logic zero. Reset clears the PRST bit.
These read/write bits select one of the seven prescaler outputs as the input to the PIT counter as
21-2
1 = PIT counter has reached modulo value
0 = PIT counter has not reached modulo value
1 = PIT overflow interrupts enabled
0 = PIT overflow interrupts disabled
1 = PIT counter stopped
0 = PIT counter active
1 = Prescaler and PIT counter cleared
0 = No effect
shows. Reset clears the PPS[2:0] bits.
Address:
Do not set the PSTOP bit before entering wait mode if the PIT is required
to exit wait mode.
Setting the PSTOP and PRST bits simultaneously stops the PIT counter at
a value of $0000.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$004B
POF
Bit 7
0
0
Figure 21-3. PIT Status and Control Register (PSC)
= Unimplemented
POIE
6
0
PSTOP
5
1
NOTE
NOTE
PRST
4
0
0
3
0
0
PPS2
2
0
PPS1
1
0
Freescale Semiconductor
PPS0
Bit 0
0
Table