MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 354

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

Byte Data Link Controller (BDLC)
27.6.1 BDLC Analog and Roundtrip Delay Register
This register programs the BDLC to compensate for various delays of different external transceivers. The
default delay value is16 μs. Timing adjustments from 9 μs to 24 μs in steps of 1 μs are available. The
BARD register can be written only once after each reset, after which they become read-only bits. The
register may be read at any time.
ATE — Analog Transceiver Enable Bit
RXPOL — Receive Pin Polarity Bit
B03–B00 — BARD Offset Bits
354
The analog transceiver enable (ATE) bit is used to select either the on-board or an off-chip analog
transceiver.
The receive pin polarity (RXPOL) bit is used to select the polarity of an incoming signal on the receive
pin. Some external analog transceivers invert the receive signal from the J1850 bus before feeding it
back to the digital receive pin.
Table 27-2
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
1 = Select normal/true polarity; true non-inverted signal from the J1850 bus; for example, the
0 = Select inverted polarity, where an external transceiver inverts the receive signal from the J1850
external transceiver does not invert the receive signal
bus
Address:
shows the expected transceiver delay with respect to BARD offset values.
This device does not contain an on-board transceiver. This bit should be
programmed to a 0 for proper operation.
Reset:
Read:
Write:
Figure 27-15. BDLC Analog and Roundtrip Delay Register (BARD)
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$003B
Bit 7
ATE
R
1
BARD Offset Bits B0[3:0]
= Reserved
RXPOL
Table 27-2. BDLC Transceiver Delay
6
1
0000
0001
0010
0011
0100
0101
0110
0111
5
0
R
0
NOTE
R
4
0
0
Transceiver’s Delays (μs)
Corresponding Expected
BO3
3
0
10
11
12
13
14
15
16
9
BO2
2
1
BO1
1
1
Freescale Semiconductor
Bit 0
BO0
1