MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 353

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

27.5.5.5 Summary
27.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and consists of five user
registers.
Freescale Semiconductor
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BDLC analog and roundtrip delay register (BARD)
BDLC control register 1 (BCR1)
BDLC control register 2 (BCR2)
BDLC state vector register (BSVR)
BDLC data register (BDR)
Transmission Error
Cyclical Redundancy Check (CRC)
Error
Invalid Symbol: BDLC Receives
Invalid Bits (Noise)
Framing Error
Bus Short to V
Bus Short to GND
BDLC Receives BREAK Symbol.
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Error Condition
DD
Table 27-1. BDLC J1850 Bus Error Summary
Figure 27-14. BDLC Block Diagram
PROTOCOL HANDLER
PHYSICAL INTERFACE
For invalid bits or framing symbols on non-byte
boundaries, invalid symbol interrupt will be
generated. BDLC stops transmission.
CRC error interrupt will be generated. The BDLC will
wait for SOF.
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
Invalid symbol interrupt will be generated. The BDLC
will wait for start-of-frame (SOF).
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical interface.
Fault condition is reflected in BSVR as an invalid
symbol.
The BDLC will wait for the next valid SOF. Invalid
symbol interrupt will be generated.
CPU INTERFACE
MUX INTERFACE
TO J1850 BUS
TO CPU
BDLC Function
BDLC
BDLC CPU Interface
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