MC908AZ60ACFUER Freescale Semiconductor, MC908AZ60ACFUER Datasheet - Page 257

• Manufacturer Part Number: MC908AZ60ACFUER
• Description: IC MCU 60K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFUER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Controller Family/series: HC08
• No. Of I/o's: 52
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC908AZ60ACFUERTR

22.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Figure 22-13
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a
logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
X = don’t care
Hi-Z = high impedance
1. Writing affects data register, but does not affect input.
shows the port D I/O logic.
DDRD
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Bit
Reset:
0
1
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
PTD
DDRD7
$0007
Bit
Bit 7
X
X
0
Figure 22-12. Data Direction Register D (DDRD)
Input, Hi-Z
DDRD6
I/O Pin
Output
Mode
6
0
Table 22-4. Port D Pin Functions
RESET
Figure 22-13. Port D I/O Circuit
DDRD5
5
0
Accesses to DDRD
Table 22-4
Read/Write
DDRD[7:0]
DDRD[7:0]
NOTE
DDRD4
DDRDx
PTDx
4
0
summarizes the operation of the port D pins.
DDRD3
3
0
PTD[7:0]
Read
Pin
DDRD2
Accesses to PTD
2
0
DDRD1
1
0
PTD[7:0]
PTD[7:0]
Write
DDRD0
Bit 0
PTDx
(1)
0
Port D
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