HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet
HD64F7144F50V
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HD64F7144F50V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7144 Group, 32 SH7145 Group Hardware Manual ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...
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The SH7144 Group and SH7145 Group single-chip RISC (Reduced Instruction Set Computer) microcomputers integrate a Renesas Technology Corp. original RISC CPU core with peripheral functions required for system configuration. Target users: This manual was written for users who will be ...
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In this manual, the product abbreviations are used to distinguish products. For example, 112- pin products are collectively referred to as the SH7144, an abbreviation of the basic type's classification code, while 144-pin products are collectively referred to as the ...
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SH7144 Group, SH7145 Group manuals: Document Title SH7144 Group, SH7145 Group Hardware Manual SH-1/SH-2/SH-DSP Software Manual User's manuals for development tools: Document Title C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual Simulator/Debugger (for Windows) User's Manual High-performance Embedded Workshop User's ...
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All trademarks and registered trademarks are the property of their respective owners. Rev.4.00 Mar. 27, 2008 Page viii of xliv REJ09B0108-0400 ...
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Section 1 Overview........................................................................................... 1 1.1 Features .............................................................................................................................2 1.2 Internal Block Diagram.....................................................................................................4 1.3 Pin Arrangement ...............................................................................................................6 1.4 Pin Functions ....................................................................................................................8 Section 2 CPU................................................................................................... 15 2.1 Features .............................................................................................................................15 2.2 Register Configuration ......................................................................................................15 2.2.1 General Registers (Rn).........................................................................................15 2.2.2 Control Registers .................................................................................................17 2.2.3 System ...
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Note on Changing Operating Mode .................................................................................. 52 Section 4 Clock Pulse Generator .......................................................................53 4.1 Oscillator........................................................................................................................... 55 4.1.1 Connecting Crystal Resonator ............................................................................. 55 4.1.2 External Clock Input Method............................................................................... 56 4.2 Function for Detecting Oscillator Halt.............................................................................. 57 4.3 Usage Notes ...................................................................................................................... ...
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Section 6 Interrupt Controller (INTC) .............................................................. 77 6.1 Features .............................................................................................................................77 6.2 Input/Output Pins ..............................................................................................................79 6.3 Register Descriptions ........................................................................................................79 6.3.1 Interrupt Control Register 1 (ICR1).....................................................................80 6.3.2 Interrupt Control Register 2 (ICR2).....................................................................82 6.3.3 IRQ Status Register (ISR)....................................................................................84 6.3.4 Interrupt Priority Registers A ...
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Usage Notes ...................................................................................................................... 111 7.5.1 Simultaneous Fetching of Two Instructions ........................................................ 111 7.5.2 Instruction Fetches at Branches ........................................................................... 111 7.5.3 Contention between User Break and Exception Processing ................................ 112 7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 112 7.5.5 ...
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Register Descriptions ........................................................................................................144 9.5.1 Bus Control Register 1 (BCR1) ...........................................................................144 9.5.2 Bus Control Register 2 (BCR2) ...........................................................................147 9.5.3 Wait Control Register 1 (WCR1).........................................................................152 9.5.4 Wait Control Register 2 (WCR2).........................................................................153 9.5.5 RAM Emulation Register (RAMER)...................................................................153 9.6 Accessing External Space .................................................................................................154 ...
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Example of DMA Transfer between External RAM and External Device with DACK .......................................................................................................... 207 10.5.3 Example of DMA Transfer between A/D Converter and On-chip Memory (Address Reload On)............................................................................................ 208 10.5.4 Example of DMA Transfer between External Memory and SCI1 ...
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DTC/DMAC Activation.......................................................................................312 11.5.3 A/D Converter Activation....................................................................................312 11.6 Operation Timing..............................................................................................................313 11.6.1 Input/Output Timing ............................................................................................313 11.6.2 Interrupt Signal Timing........................................................................................318 11.7 Usage Notes ......................................................................................................................321 11.7.1 Module Standby Mode Setting.............................................................................321 11.7.2 Input Clock Restrictions.......................................................................................321 11.7.3 Caution on Period Setting ....................................................................................322 11.7.4 Contention between ...
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Operation ............................................................................................................. 375 11.9.5 Usage Notes ......................................................................................................... 377 Section 12 Watchdog Timer (WDT) .................................................................379 12.1 Features............................................................................................................................. 379 12.2 Input/Output Pin................................................................................................................ 380 12.3 Register Descriptions ........................................................................................................ 381 12.3.1 Timer Counter (TCNT)........................................................................................ 381 12.3.2 Timer Control/Status Register (TCSR)................................................................ 382 12.3.3 Reset ...
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Operation in Asynchronous Mode ....................................................................................426 13.4.1 Data Transfer Format ...........................................................................................427 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ....................................................................................................................428 13.4.3 Clock....................................................................................................................429 13.4.4 SCI Initialization (Asynchronous Mode) .............................................................430 13.4.5 Data Transmission (Asynchronous Mode)...........................................................431 13.4.6 Serial Data Reception ...
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Section Bus Interface (IIC) Option.........................................................467 14.1 Features............................................................................................................................. 468 14.2 Input/Output Pins .............................................................................................................. 470 14.3 Description of Registers.................................................................................................... 471 2 14.3 Bus Data Register (ICDR) ............................................................................. 471 14.3.2 Slave-Address Register (SAR)............................................................................. 472 14.3.3 Second Slave-Address ...
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External Trigger Input Timing .............................................................................552 15.5 Interrupt Sources and DTC, DMAC Transfer Requests....................................................553 15.6 Definitions of A/D Conversion Accuracy .........................................................................554 15.7 Usage Notes ......................................................................................................................556 15.7.1 Module Standby Mode Setting.............................................................................556 15.7.2 Permissible Signal Source Impedance .................................................................556 15.7.3 Influences on Absolute ...
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Port D Control Registers L1, L2, H1, H2 (PDCRL1, PDCRL2, PDCRH1, PDCRH2)......................................................... 612 17.1.9 Port E I/O Register L (PEIORL).......................................................................... 621 17.1.10 Port E Control Registers L1, L2 (PECRL1, PECRL2) ........................................ 622 17.1.11 High-Current Port Control Register (PPCR)........................................................ 630 ...
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Programming/Erasing in User Program Mode.....................................................673 19.7 Flash Memory Emulation in RAM....................................................................................674 19.8 Flash Memory Programming/Erasing ...............................................................................676 19.8.1 Program/Program-Verify Mode ...........................................................................676 19.8.2 Erase/Erase-Verify Mode.....................................................................................678 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................678 19.9 Program/Erase Protection..................................................................................................680 19.9.1 Hardware Protection ............................................................................................680 19.9.2 Software ...
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Section 23 Advanced User Debugger (AUD) ...................................................705 23.1 Overview........................................................................................................................... 705 23.1.1 Features................................................................................................................ 705 23.1.2 Block Diagram..................................................................................................... 706 23.2 Input/Output Pins .............................................................................................................. 707 23.2.1 Pin Descriptions................................................................................................... 707 23.3 Branch Trace Mode........................................................................................................... 710 23.3.1 Overview.............................................................................................................. 710 23.3.2 Operation ............................................................................................................. 710 23.4 RAM ...
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Section 25 List of Registers .............................................................................. 733 25.1 Register Address Table (In the Order from Lower Addresses).........................................734 25.2 Register Bit List ................................................................................................................745 25.3 Register States in Each Operating Mode...........................................................................758 Section 26 Electrical Characteristics ................................................................ 767 26.1 Absolute Maximum Ratings .............................................................................................767 ...
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Index .........................................................................................................879 Rev.4.00 Mar. 27, 2008 Page xxiv of xliv REJ09B0108-0400 ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of SH7144...............................................................................4 Figure 1.2 Block Diagram of SH7145 ............................................................................................5 Figure 1.3 SH7144 Pin Arrangement..............................................................................................6 Figure 1.4 SH7145 Pin Arrangement..............................................................................................7 Section 2 CPU Figure 2.1 CPU Internal Registers ................................................................................................16 Figure 2.2 Data Format ...
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Figure 8.5 DTC Operation Flowchart......................................................................................... 126 Figure 8.6 Memory Mapping in Normal Mode .......................................................................... 127 Figure 8.7 Memory Mapping in Repeat Mode ........................................................................... 128 Figure 8.8 Memory Mapping in Block Transfer Mode............................................................... 130 Figure 8.9 Chain Transfer........................................................................................................... 131 Figure 8.10 ...
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Figure 10.11 DMA Transfer Example in Cycle-Steal Mode ......................................................195 Figure 10.12 DMA Transfer Example in Burst Mode ................................................................195 Figure 10.13 Bus Handling when Multiple Channels Are Operating .........................................197 Figure 10.14 Cycle Steal, Dual Address and Level Detection (Fastest Operation) ....................200 ...
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Figure 11.25 Example of Phase Counting Mode 1 Operation .................................................... 277 Figure 11.26 Example of Phase Counting Mode 2 Operation .................................................... 278 Figure 11.27 Example of Phase Counting Mode 3 Operation .................................................... 279 Figure 11.28 Example of Phase Counting Mode ...
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Figure 11.57 Output Compare Output Timing (Normal Mode/PWM Mode).............................314 Figure 11.58 Output Compare Output Timing (Complementary PWM Mode/ Reset Synchronous PWM Mode) ..........................................................................315 Figure 11.59 Input Capture Input Signal Timing........................................................................315 Figure 11.60 Counter Clear Timing (Compare Match)...............................................................316 Figure 11.61 Counter ...
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Figure 11.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode........................... 345 Figure 11.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 .......................... 346 Figure 11.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode ...
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Section 12 Watchdog Timer (WDT) Figure 12.1 Block Diagram of WDT ..........................................................................................380 Figure 12.2 Operation in Watchdog Timer Mode.......................................................................386 Figure 12.3 Operation in Interval Timer Mode...........................................................................386 Figure 12.4 Timing of Setting OVF............................................................................................387 Figure 12.5 Timing of Setting WOVF ........................................................................................388 Figure ...
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Figure 13.22 Normal Smart Card Interface Data Format ........................................................... 452 Figure 13.23 Direct Convention (DIR = SINV = O/E = 0)......................................................... 452 Figure 13.24 Inverse Convention (DIR = SINV = O/E = 1)....................................................... 453 Figure 13.25 Receive Data Sampling Timing ...
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Figure 14.19 An Example of the Timing of Operations in Slave Receive Mode 2 (MLS = 0, HNDS = 1)...........................................................................................513 Figure 14.20 Example: Flowchart of Operations in Slave Transmit Mode (HNDS = 0)............514 Figure 14.21 An Example of the Timing ...
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Section 18 I/O Ports Figure 18.1 Port A (SH7144)...................................................................................................... 634 Figure 18.2 Port A (SH7145)...................................................................................................... 635 Figure 18.3 Port B....................................................................................................................... 639 Figure 18.4 Port C....................................................................................................................... 642 Figure 18.5 Port D (SH7144)...................................................................................................... 645 Figure 18.6 Port D (SH7145)...................................................................................................... 646 Figure 18.7 ...
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Figure 23.5 Example of Read Operation (Byte Read) ................................................................714 Figure 23.6 Example of Write Operation (Longword Write) .....................................................714 Figure 23.7 Example of Error Occurrence (Longword Read).....................................................714 Section 24 Power-Down Modes Figure 24.1 NMI Timing in Software Standby Mode (Application Example) ...
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Figure D.4 PAn/TCLKm/CSx .................................................................................................... 816 Figure D.5 PAn/TCLKm/IRQx .................................................................................................. 817 Figure D.6 PAn/Function 1......................................................................................................... 818 Figure D.7 PA15/CK .................................................................................................................. 819 Figure D.8 PA16/AUDSYNC..................................................................................................... 820 Figure D.9 PA17/WAIT ............................................................................................................. 821 Figure D.10 PA18/BREQ/DRAK0............................................................................................. 822 Figure D.11 PA19/BACK/DRAK1 ............................................................................................ 823 Figure D.12 ...
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Figure D.44 PE1/TIOC0B/DRAK0/TRST .................................................................................856 Figure D.45 PE3/TIOC0D/DRAK1/TDO...................................................................................857 Figure D.46 PE0/TIOC0A/DREQ0/AUDCK .............................................................................858 Figure D.47 PE1/TIOC0B/DRAK0/AUDMD ............................................................................859 Figure D.48 PE2/TIOC0C/DREQ1/AUDRST............................................................................860 Figure D.49 PEn/TIOCxx/Function 1/AUDATAm....................................................................861 Figure D.50 PE4/TIOC1A/RXD3/AUDATA2...........................................................................862 Figure D.51 PE6/TIOC2A/SCK3/AUDATA0............................................................................863 Figure D.52 PE8/TIOC3A/SCK2/TMS ......................................................................................864 Figure D.53 PE9/TIOC3B/SCK3/TRST.....................................................................................865 Figure D.54 PE10/TIOC3C/TXD2/TDI .....................................................................................866 Figure ...
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Rev.4.00 Mar. 27, 2008 Page xxxviii of xliv REJ09B0108-0400 ...
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Section 2 CPU Table 2.1 Initial Values of Registers.......................................................................................18 Table 2.2 Sign Extension of Word Data .................................................................................21 Table 2.3 Delayed Branch Instructions...................................................................................22 Table 2.4 T Bit ........................................................................................................................22 Table 2.5 Immediate Data Accessing......................................................................................23 Table 2.6 Absolute Address Accessing...................................................................................23 Table 2.7 Displacement ...
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Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs ................. 124 Table 8.2 Normal Mode Register Functions ......................................................................... 127 Table 8.3 Repeat Mode Register Functions .......................................................................... 128 Table 8.4 Block Transfer Mode Register ...
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Table 11.13 TIOR_2 (Channel 2) .............................................................................................231 Table 11.14 TIORH_3 (Channel 3) ..........................................................................................232 Table 11.15 TIORL_3 (Channel 3)...........................................................................................233 Table 11.16 TIORH_4 (Channel 4) ..........................................................................................234 Table 11.17 TIORL_4 (Channel 4)...........................................................................................235 Table 11.18 TIORH_0 (Channel 0) ..........................................................................................236 Table 11.19 TIORL_0 (Channel 0)...........................................................................................237 Table ...
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Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 418 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 418 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 419 Table ...
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Section 17 Pin Function Controller (PFC) Table 17.1 SH7144 Multiplexed Pins (Port A) .......................................................................569 Table 17.2 SH7144 Multiplexed Pins (Port B) .......................................................................570 Table 17.3 SH7144 Multiplexed Pins (Port C) .......................................................................570 Table 17.4 SH7144 Multiplexed Pins (Port D) .......................................................................571 Table 17.5 ...
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Section 24 Power-Down Modes Table 24.1 Internal Operation States in Each Mode ............................................................... 720 Table 24.2 Pin Configuration.................................................................................................. 721 Section 26 Electrical Characteristics Table 26.1 Absolute Maximum Ratings ................................................................................. 767 Table 26.2 DC Characteristics ................................................................................................ 768 Table 26.3 Permitted Output ...
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The SH7144 Group and SH7145 Group single-chip RISC (Reduced Instruction Set Computer) microcomputers integrate a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The SH7144 Group and SH7145 Group CPU has a RISC-type instruction set. ...
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Overview 1.1 Features • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture ⎯ Instruction length: 16-bit fixed length for improved code efficiency ⎯ Load-store architecture (basic operations are executed between registers) ⎯ Sixteen 32-bit ...
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On-chip memory ROM Part No. Flash memory version HD64F7144F50 HD64F7145F50 Masked ROM version HD6437144F50 HD6437145F50 ROM less version HD6417144F50 HD6417145F50 • I/O ports Part No. HD64F7144F50/ HD6437144F50/ HD6417144F50 HD64F7145F50/ HD6437145F50/ HD6417145F50 • Supports various power-down states • Compact package ...
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Overview 1.2 Internal Block Diagram RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcc P PLLCAP L L PLLVss FWP* Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss AVcc AVss DBGMD ASEBRKAK Note: ...
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RES WDTOVF MD3 MD2 MD1 AUD* MD0 NMI EXTAL XTAL PLLVcc P L PLLCAP L PLLVss CPU FWP* Vcc Vcc Vcc Interrupt controller Vcc Vcc Vcc Serial communication Vcc interface (× 4 channels) Vss Vss Vss Compare match timer Vss ...
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Overview 1.3 Pin Arrangement PE0/TIOC0A/DREQ0/TMS PE1/TIOC0B/DRAK0/TRST * 86 ...
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PE0/TIOC0A/DREQ0/AUDCK* 109 4 PE1/TIOC0B/DRAK0/AUDMD* 110 ...
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Overview 1.4 Pin Functions Type Symbol Power V CC Supply V SS Clock PLLV CC PLLV SS PLLCAP EXTAL XTAL CK Operating MD3 to MD0 mode control FWP Rev.4.00 Mar. 27, 2008 Page 8 of 882 REJ09B0108-0400 I/O Name ...
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Type Symbol RES System control MRES WDTOVF BREQ BACK Interrupts NMI IRQ7 to IRQ0 Input IRQOUT Address bus A21 to A0 Data bus SH7144: D15 to D0 SH7145: D31 to D0 I/O Name Function Input Power on When this pin ...
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Overview Type Symbol CS3 to CS0 Bus control CS5, CS4 (SH7145 masked ROM version and ROM less version only) CS7, CS6 (masked ROM version and ROM less version only) RD WRHH (SH7145 only) WRHL (SH7145 only) WRH WRL WAIT ...
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Type Symbol Multifunction TCLKA to timer-pulse TCLKD unit (MTU) TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A to TIOC3D TIOC4A to TIOC4D Serial TXD3 to communication TXD0 interface (SCI) RXD3 to RXD0 SCK3 to SCK0 bus SCL0 ...
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Overview Type Symbol POE3 to Output control POE0 for MTU A/D AN7 to AN0 Input converter ADTRG AVref (SH7145 only I/O port SH7144 PA15 to PA0 SH7145 PA23 to PA0 PB9 to PB0 Input/ PC15 ...
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Type Symbol User TCK debugging TMS interface (H-UDI) TDI (flash version only) TDO TRST Advanced AUDATA3 to user debugger AUDATA0 (AUD) (flash version only) AUDRST AUDMD AUDCK AUDSYNC ASEBRKAK Output E10 interface (flash version only) DBGMD [Caution] Do not pull-down ...
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Overview Rev.4.00 Mar. 27, 2008 Page 14 of 882 REJ09B0108-0400 ...
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Features • General-register architecture ⎯ Sixteen 32-bit general registers • Sixty-two basic instructions • Eleven addressing modes ⎯ Register direct [Rn] ⎯ Register indirect [@Rn] ⎯ Register indirect with post-increment [@Rn+] ⎯ Register indirect with pre-decrement [@-Rn] ⎯ Register ...
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CPU General registers (Rn) Status register (SR) Global base register (GBR) Vector base register (VBR) Multiply-accumulate register (MAC) Procedure register Program counter (PC) Notes functions as an index register in the indirect indexed register addressing mode and ...
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Control Registers The control registers consist of three 32-bit registers: status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the ...
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CPU Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. Vector Base Register (VBR): ...
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Data Formats 2.3.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits word (16 bits changed into a longword by expanding the ...
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CPU 2.3.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the ...
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Instruction Features 2.4.1 RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per State: The microcomputer can execute basic instructions ...
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CPU Table 2.3 Delayed Branch Instructions CPU of This LSI BRA TRGET ADD R1,R0 Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations are executed in one and two states. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate operations ...
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Table 2.5 Immediate Data Accessing Classification CPU of This LSI 8-bit immediate MOV 16-bit immediate MOV.W .DATA.W 32-bit immediate MOV.L .DATA.L Note: @(disp, PC) accesses the immediate data. Absolute Address: When data is accessed by absolute address, the value in ...
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CPU Table 2.7 Displacement Accessing Classification CPU of This LSI 16-bit displacement MOV.W MOV.W .DATA.W Note: @(disp,PC) accesses the immediate data. Rev.4.00 Mar. 27, 2008 Page 24 of 882 REJ09B0108-0400 Example of Conventional CPU @(disp,PC),R0 MOV.W @(R0,R1),R2 .................. H'1234 ...
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Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Direct register Rn addressing Indirect register @Rn addressing Post-increment @Rn+ indirect register addressing Pre-decrement @-Rn indirect register ...
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CPU Addressing Instruction Mode Format Indirect register @(disp:4, addressing with Rn) displacement Indirect indexed @(R0, Rn) The effective address is the sum of Rn and R0. register addressing Indirect GBR @(disp:8, addressing with GBR) displacement Indirect indexed @(R0, GBR ...
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Addressing Instruction Mode Format Indirect PC @(disp:8, addressing with PC) displacement PC relative disp:8 addressing disp:12 Rn Effective Address Calculation The effective address is the sum of PC value and an 8-bit displacement (disp). The value of disp is zero-extended, ...
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CPU Addressing Instruction Mode Format Immediate #imm:8 addressing #imm:8 #imm:8 Rev.4.00 Mar. 27, 2008 Page 28 of 882 REJ09B0108-0400 Effective Address Calculation The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. The 8-bit ...
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Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source ...
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CPU Instruction Formats nm format 15 0 xxxx nnnn xxxx mmmm md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 0 xxxx xxxx nnnn dddd nmd format 15 0 xxxx dddd nnnn mmmm Rev.4.00 Mar. 27, 2008 ...
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Instruction Formats d format 15 0 xxxx xxxx dddd dddd d12 format 15 0 xxxx dddd dddd dddd nd8 format 15 0 xxxx nnnn dddd dddd i format 15 0 xxxx xxxx ...
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CPU 2.5 Instruction Set 2.5.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA MOVT SWAP XTRCT Arithmetic 21 ADD operations ...
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Operation Classification Types Code Arithmetic SUBC operations SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR RTS ...
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CPU Operation Classification Types Code System 11 CLRT control CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 Rev.4.00 Mar. 27, 2008 Page 34 of 882 REJ09B0108-0400 Function T bit clear MAC register clear Load to ...
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The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. • Instruction Code Format Item Format Instruction Described in mnemonic. OP.Sz SRC,DEST Described in MSB ↔ ...
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CPU • Data Transfer Instructions Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L @(disp,PC),Rn 1101nnnndddddddd MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L ...
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Instruction Instruction Code MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 MOV.B R0,@(disp,GBR) 11000000dddddddd MOV.W R0,@(disp,GBR) 11000001dddddddd MOV.L R0,@(disp,GBR) 11000010dddddddd MOV.B @(disp,GBR),R0 11000100dddddddd MOV.W @(disp,GBR),R0 11000101dddddddd MOV.L @(disp,GBR),R0 11000110dddddddd MOVA @(disp,PC),R0 11000111dddddddd MOVT Rn 0000nnnn00101001 SWAP.B Rm,Rn 0110nnnnmmmm1000 SWAP.W ...
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CPU • Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL ...
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Instruction Instruction Code DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB ...
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CPU • Logic Operation Instructions Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) 11001101iiiiiiii NOT Rm,Rn OR Rm,Rn OR #imm,R0 OR.B #imm,@(R0,GBR) 11001111iiiiiiii TAS.B @Rn TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) 11001100iiiiiiii XOR Rm,Rn XOR #imm,R0 XOR.B #imm,@(R0,GBR) 11001110iiiiiiii Rev.4.00 ...
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Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 SHLR8 ...
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CPU • Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 ...
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System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH ...
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CPU Instruction Instruction Code TRAPA #imm 11000011iiiiiiii Note: * The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when (1) ...
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Processing States 2.6.1 State Transitions The CPU has five processing states: reset, exception processing, bus release, program execution and power-down. Figure 2.4 shows the transitions between the states. From any state when RES = 0 When an internal power-on ...
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CPU Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state ...
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Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has four operating modes and four clock modes. The operating mode is determined by the setting of MD3 to MD0, and FWP pins. Do not set these pins ...
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MCU Operating Modes The clock mode is selected by the input of MD2 and MD3 pins. Table 3.2 Clock Mode Setting Pin Setting Clock Mode No. MD3 Note: The maximum clock ...
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Input/Output Pins Table 3.3 describes the configuration of operating mode related pin. Table 3.3 Pin Configuration Pin Name Input/Output MD0 Input MD1 Input MD2 Input MD3 Input FWP Input Function Designates operating mode through the level applied to this ...
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MCU Operating Modes 3.3 Operating Modes 3.3.1 Mode 0 (MCU Extension Mode 0) CS0 space and CS4 space become external memory spaces with 8-bit bus width in SH7144 or 16- bit bus width in SH7145. 3.3.2 Mode 1 (MCU ...
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Address Map The address map for the operating modes are shown in figure 3.1. Modes 0 and 1 On-chip ROM disabled mode H'00000000 CS0 space H'003FFFFF H'00400000 CS1 space H'007FFFFF H'00800000 CS2 space H'00BFFFFF H'00C00000 CS3 space H'00FFFFFF H'01000000 ...
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MCU Operating Modes 3.5 Initial State in This LSI In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to ...
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Section 4 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and the peripheral clock (Pφ), and then makes internal clock (φ/2 to φ/8192 and Pφ/2 to Pφ/1024) out of this ...
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Clock Pulse Generator Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating clock System clock (φ) Peripheral clock (Pφ) Rev.4.00 Mar. 27, 2008 Page 54 of 882 REJ09B0108-0400 Operating Module CPU ...
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Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.2. ...
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Clock Pulse Generator Table 4.3 Crystal Resonator Characteristics Frequency (MHz) Rs max (Ω) C max (pF) 0 4.1.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external ...
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Function for Detecting Oscillator Halt This CPG can detect a clock halt and automatically cause the timer pins to become high- impedance when any system abnormality causes the oscillator to halt. That is, when a change of EXTAL has ...
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Clock Pulse Generator 4.3 Usage Notes 4.3.1 Note on Crystal Resonator A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to ...
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A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate the PLL power lines ...
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Clock Pulse Generator Rev.4.00 Mar. 27, 2008 Page 60 of 882 REJ09B0108-0400 ...
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Section 5 Exception Processing 5.1 Overview 5.1.1 Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exception processing sources ...
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Exception Processing 3. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, and BRAF. 5.1.2 Exception Processing Operations The exception processing sources are detected and begin processing according to the timing ...
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Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the ...
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Exception Processing Exception Sources Trap instruction (user vector) Interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 2 On-chip peripheral module* Notes: 1. Only in the F-ZTAT version. 2. The vector numbers and vector table address offsets for each ...
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Resets 5.2.1 Types of Reset Resets have the highest priority of any exception source. There are two types of resets: manual resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of the ...
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Exception Processing 4. The values fetched from the exception processing vector table are set in PC and SP, then the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. Power-On Reset ...
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Address Errors 5.3.1 Cause of Address Error Exception Address errors occur when instructions are fetched or data read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle ...
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Exception Processing 5.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends, the current instruction finishes, and then address error exception processing starts. The CPU operates as follows: 1. ...
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Interrupts 5.4.1 Interrupt Sources Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type NMI User break H-UDI IRQ On-chip peripheral module ...
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Exception Processing 5.4.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception processing according to the results. The priority order ...
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Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions ...
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Exception Processing 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called “instruction placed in a delay slot”. When the instruction placed in the delay slot is an undefined code, illegal slot exception processing ...
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Cases when Exception Sources Are not Accepted When an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction sometimes not accepted immediately but stored instead, as shown in table 5.10. In ...
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Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is shown in table 5.11. Table 5.11 Stack Status after Exception Processing Ends Types Address error Trap instruction General illegal instruction ...
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Usage Notes 5.8.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed during exception processing. 5.8.2 ...
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Exception Processing Rev.4.00 Mar. 27, 2008 Page 76 of 882 REJ09B0108-0400 ...
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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features • 16 levels of interrupt priority • NMI noise canceler function • Occurrence of interrupt can ...
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Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 (Interrupt request) UBC (Interrupt request) DMAC (Interrupt request) H-UDI (Interrupt request) DTC (Interrupt request) MTU (Interrupt request) ...
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Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin 6.3 Register Descriptions The interrupt controller has the following registers. For details on ...
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Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins NMI and IRQ0 to IRQ7 and indicates the input signal level at ...
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Bit Bit Name Initial Value 4 IRQ3S 0 3 IRQ4S 0 2 IRQ5S 0 1 IRQ6S 0 0 IRQ7S 0 R/W Description R/W IRQ3 Sense Select This bit sets the IRQ3 interrupt request detection mode. 0: Interrupt request is detected ...
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Interrupt Controller (INTC) 6.3.2 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0 to IRQ7. ICR2 is, however, valid only when IRQ interrupt request detection ...
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Bit Bit Name Initial Value 9 IRQ3ES1 0 8 IRQ3ES0 0 7 IRQ4ES1 0 6 IRQ4ES0 0 5 IRQ5ES1 0 4 IRQ5ES0 0 3 IRQ6ES1 0 2 IRQ6ES0 0 R/W Description R/W This bit sets the IRQ3 interrupt request edge ...
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Interrupt Controller (INTC) Bit Bit Name Initial Value 1 IRQ7ES1 0 0 IRQ7ES0 0 6.3.3 IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ7. ...
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Interrupt Priority Registers (IPRA to IPRJ) Interrupt priority registers are ten 16-bit readable/writable registers that set priority levels from for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer ...
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Interrupt Controller (INTC) Bit Bit Name Initial Value 7 IPR7 0 6 IPR6 0 5 IPR5 0 4 IPR4 0 3 IPR3 0 2 IPR2 0 1 IPR1 0 0 IPR0 0 Note: Name in the tables above is ...
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Interrupt Sources There are five types of interrupt sources: NMI, user breaks, H-UDI, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). ...
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Interrupt Controller (INTC) Level IRQ pins detection Edge detection RESIRQn (Acceptance of IRQn interrupt/DTC transfer end/ writing 0 after reading IRQnF = 1) Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip ...
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H-UDI Interrupt The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs when an H- UDI interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are held until accepted. H-UDI exception ...
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Interrupt Controller (INTC) 6.5 Interrupt Exception Processing Vectors Table Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. ...
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Interrupt Source Name DMAC DEI0 DEI1 DEI2 DEI3 MTU channel 0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 MTU channel 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 MTU channel 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 MTU channel 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 MTU channel ...
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Interrupt Controller (INTC) Interrupt Source Name SCI channel 1 ERI_1 RXI_1 TXI_1 TEI_1 A/D ADI0 ADI1 DTC SWDTEND CMT CMI0 CMI1 Watchdog ITI timer ⎯ Reserved by system 153 I/O (MTU) MTUOEI ⎯ Reserved by system 160 to SCI ...
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Operation 6.6.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the ...
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Interrupt Controller (INTC) the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. Program execution state No Interrupt? Yes No NMI? Yes User break? Yes *1 IRQOUT ...
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Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n–8 4n–4 4n Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always make sure that ...
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Interrupt Controller (INTC) 6.7 Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the ...
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IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address ...
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Interrupt Controller (INTC) 6.8 Data Transfer with Interrupt Request Signals The following data transfers can be done using interrupt request signals: • Activate DMAC only, CPU interrupts do not occur • Activate DTC only, CPU interrupts according to DTC ...
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Handling Interrupt Request Signals as Sources for DTC Activating and CPU Interrupt, but Not DMAC Activating 1. Do not select DMAC activating sources or clear the DTE bit For DTC, set the corresponding DTE bits and ...
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Interrupt Controller (INTC) 6.8.4 Handling Interrupt Request Signals as Source for CPU Interrupt but Not DMAC and DTC Activating 1 Do not select DMAC activating sources or clear the DME bit For DTC, clear the corresponding ...
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Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that make program debugging easier. By setting break conditions in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated ...
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User Break Controller (UBC) Figure 7.1 shows a block diagram of the UBC. Module bus UBBR UBCR Break condition [Legend] UBARH, UBARL: User break address registers H, L UBAMRH, UBAMRL: User break address mask registers H, L UBBR: User ...
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Register Descriptions The UBC has the following registers. For details on register addresses and register states during each processing, refer to section 25, List of Registers. • User break address register H (UBARH) • User break address register L ...
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User Break Controller (UBC) Bit Bit Name UBAMRH15 to UBM31 to UBAMRH0 UBM16 UBAMRL15 to UBM15 to UBAMRL0 UBM0 7.2.3 User Break Bus Cycle Register (UBBR) The user break bus cycle register (UBBR 16-bit readable/writable register that ...
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Bit Bit Name Initial Value 3 RW1 0 2 RW0 0 1 SZ1 0 0 SZ0 0 Note: When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are * considered to be accessed in word-size ...
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User Break Controller (UBC) 7.3 Operation 7.3.1 Flow of User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break ...
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UBARH/UBARL Internal address bits 31–0 CP1 CPU cycle DMAC/DTC cycle ID1 Instruction fetch Data access RW1 Read cycle Write cycle SZ1 Byte size Word size Longword size Figure 7.2 Break Condition Determination Method UBAMRH/UBAMRL CP0 ID0 ...
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User Break Controller (UBC) 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle Data in on-chip memory (on-chip ROM and/or RAM) is always accessed as 32-bits data in one bus cycle. Therefore, two instructions can be retrieved in one bus ...
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Examples of Use Break on CPU Instruction Fetch Cycle 1. Register settings: UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size is not included ...
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User Break Controller (UBC) Break on CPU Data Access Cycle 1. Register settings: UBARH = H'0012 UBARL = H'3456 UBBR = H'006A UBCR = H'0000 Conditions set: Address: H'00123456 Bus cycle: CPU, data access, write, word Interrupt requests enabled ...
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Usage Notes 7.5.1 Simultaneous Fetching of Two Instructions Two instructions may be simultaneously fetched in instruction fetch operation. Once a break condition is set on the latter of these two instructions, a user break interrupt will occur before the ...
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User Break Controller (UBC) 7.5.3 Contention between User Break and Exception Processing If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and ...
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Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC’s register information ...
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Data Transfer Controller (DTC) On-chip ROM On-chip RAM On-chip peripheral module CPU interrupt request source clear control Interrupt request External memory External device (memory- mapped) [Legend] DTMR: DTC mode register DTCR: DTC transfer count register DTSAR: DTC source address ...
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Register Descriptions The DTC has the following registers. • DTC mode register (DTMR) • DTC source address register (DTSAR) • DTC destination address register (DTDAR) • DTC initial address register (DTIAR) • DTC transfer count register A (DTCRA) • ...
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Data Transfer Controller (DTC) 8.2.1 DTC Mode Register (DTMR) DTMR is a 16-bit register that selects the DTC operating mode. Bit Bit Name Initial Value 15 SM1 Undefined 14 SM0 Undefined 13 DM1 Undefined 12 DM0 Undefined 11 MD1 ...
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Bit Bit Name Initial Value 7 DTS Undefined 6 CHNE Undefined 5 DISEL Undefined 4 NMIM Undefined — Undefined [Legend] x: Don’t care 8. Data Transfer Controller (DTC) R/W Description — DTC Transfer Mode Select Specifies whether ...
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Data Transfer Controller (DTC) 8.2.2 DTC Source Address Register (DTSAR) The DTC source address register (DTSAR 32-bit register that specifies the DTC transfer source address. For the word size transfer, specify an even source address. For the ...
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The initial value of DTCRA is undefined. 8.2.6 DTC Transfer Count Register B (DTCRB) The DTCRB is a 16-bit register that designates the block length in block transfer mode. The block length is 1 when the set value is H'0001, ...
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Data Transfer Controller (DTC) 8.2.8 DTC Control/Status Register (DTCSR) DTCSR is a 16-bit readable/writable register that is used to disable/enable DTC activation by software and to set the DTC vector addresses for software activation. It also indicates the DTC ...
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Bit Bit Name Initial Value 7 DTVEC7 0 6 DTVEC6 0 5 DTVEC5 0 4 DTVEC4 0 3 DTVEC3 0 2 DTVEC2 0 1 DTVEC1 0 0 DTVEC0 0 Notes: 1. For the NMIF and AE bits, only a 0 ...
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Data Transfer Controller (DTC) 8.3 Operation 8.3.1 Activation Sources The DTC operates when activated by an interrupt write to DTCSR by software. An interrupt request can be directed to the CPU or DTC, as designated by ...
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Memory space Register information DTCRA start address DTSAR DTDAR Normal mode Figure 8.3 DTC Register Information Allocation in Memory Space Figure 8.4 shows the correspondence between DTC vector addresses and register information allocation. For each DTC activating source there are ...
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Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs Activating Source Activating Generator Source MTU (CH4) TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 MTU (CH3) TGIA_3 TGIB_3 TGIC_3 TGID_3 MTU (CH2) TGIA_2 TGIB_2 MTU (CH1) TGIA_1 ...
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Activating Source Activating Generator Source SCI0 RXI_0 TXI_0 SCI1 RXI_1 TXI_1 Reserved — A/D converter ADI1 (CH1) Reserved — SCI2 RXI_2 TXI_2 SCI3 RXI_3 TXI_3 Reserved — IIC ICI Reserved — Software Write to DTCSR Note: * External memory, memory-mapped ...
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Data Transfer Controller (DTC) The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates the transfer destination address. After each transfer, DTSAR and DTDAR are independently incremented, decremented, or left fixed depending on its register ...
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Normal Mode: Performs the transfer of one byte, one word, or one longword for each activation. The total transfer count 65536. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.2 ...
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Data Transfer Controller (DTC) Table 8.3 Repeat Mode Register Functions Register Function DTMR Operation mode control DTCRAH Transfer count save DTCRAL Transfer count DTIAR Initial address DTSAR Transfer source address DTDAR Transfer destination address DTSAR or Repeat area DTDAR ...
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Block Transfer Mode: Performs the transfer of one block for each one activation. Either the transfer source or transfer destination is designated as the block area. The block length is specified between 1 and 65536. When the transfer of one ...
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Data Transfer Controller (DTC) First block DTSAR or DTDAR Nth block Figure 8.8 Memory Mapping in Block Transfer Mode Chain Transfer: Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in a ...
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DTC vector Register information start address address Figure 8.9 Chain Transfer 8. Data Transfer Controller (DTC) Register information CHNE = 1 Register information CHNE = 0 Rev.4.00 Mar. 27, 2008 Page 131 of 882 Source Destination Source Destination REJ09B0108-0400 ...
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Data Transfer Controller (DTC) 8.3.4 Interrupt Source An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers data transfer for which the DISEL bit was set ...
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DTC Execution State Counts Table 8.5 shows the execution state for one DTC data transfer. Furthermore, table 8.6 shows the state counts needed for execution state. Table 8.5 Execution State of DTC Mode Vector Read I Normal 1 Repeat ...
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Data Transfer Controller (DTC) 8.4 Procedures for Using DTC 8.4.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in memory ...
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DTC Use Example The following is a DTC use example of a 128-byte data reception by the SCI: 1. The settings are: DTMR source address fixed (SM1 = SM0 = 0), destination address incremented (DM1 = 1, DM0 = ...
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Data Transfer Controller (DTC) 8.5 Usage Notes 8.5.1 Prohibition against DMAC/DTC Register Access by DTC DMAC and DTC register access by the DMAC is prohibited. 8.5.2 Module Standby Mode Setting DTC operation can be disabled or enabled using the ...
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Section 9 Bus State Controller (BSC) The bus state controller (BSC) divides up the address spaces and outputs control signals for various types of memory. This enables memories like SRAM and ROM to be connected directly to the chip without ...
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Bus State Controller (BSC) Figure 9.1 shows the BSC block diagram. WAIT CS0 to CS7 RD WRHH, WRHL WRH, WRL WCR1: WCR2: BCR1: BCR2: RAMER: RAM emulation register Note: Refer to section 19, Flash Memory (F-ZTAT Version), for RAMER. ...
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Input/Output Pins Table 9.1 shows the bus state controller pin configuration. Table 9.1 Pin Configuration Name Abbr. Address bus A21 to A0 Data bus D31 to D0 CS0 to CS7* Output Chip select signal indicating the area being Chip ...
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Bus State Controller (BSC) 9.3 Register Configuration The BSC has five registers. For details on these register addresses and register states in each processing states, refer to section 25, List of Registers. These registers are used to control wait ...
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Address Map Figure 9.2 shows the address format used by this LSI. A31 to A24 A23, A22 Space selection: Not output externally; used to select the type of space On-chip ROM space or CS space when 00000000 or 00000001 ...
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Bus State Controller (BSC) Table 9.2 Address Map • On-chip ROM enabled mode Address H'00000000 to H'0003FFFF H'00040000 to H'001FFFFF H'00200000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF H'01000000 to H'011FFFFF H'01200000 to H'013FFFFF H'01400000 ...
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On-chip ROM disabled mode Address H'00000000 to H'003FFFFF H'00400000 to H'007FFFFF H'00800000 to H'00BFFFFF H'00C00000 to H'00FFFFFF H'01000000 to H'013FFFFF H'01400000 to H'017FFFFF H'01800000 to H'01BFFFFF H'01C00000 to H'01FFFFFF H'02000000 to H'FFFF7FFF H'FFFF8000 to H'FFFFBFFF H'FFFFC000 to H'FFFFDFFF H'FFFFE000 ...
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Bus State Controller (BSC) 9.5 Register Descriptions 9.5.1 Bus Control Register 1 (BCR1) BCR1 is a 16-bit readable/writable register that enables access to the MTU control registers and specifies the bus size of each CS space. When using the ...
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Bit Bit Name Initial Value R/W 6 A2LG 0 5 A1LG 0 4 A0LG 0 3 A3SZ 1 Description R/W CS2 and CS6 space longword This bit specifies the CS2 and CS6 space bus size. This bit is valid only ...
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Bus State Controller (BSC) Bit Bit Name Initial Value R/W 2 A2SZ 1 1 A1SZ 1 0 A0SZ 1 Rev.4.00 Mar. 27, 2008 Page 146 of 882 REJ09B0108-0400 Description R/W CS2 and CS6 space size This bit specifies the ...
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Bus Control Register 2 (BCR2) BCR2 is a 16-bit readable/writable register that specifies the number of idle cycles and CS signal assert extension of each CS space. Bit Bit Name Initial Value R/W 15 IW31 1 14 IW30 1 ...
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Bus State Controller (BSC) Bit Bit Name Initial Value R/W 11 IW11 1 10 IW10 1 9 IW01 1 8 IW00 1 Rev.4.00 Mar. 27, 2008 Page 148 of 882 REJ09B0108-0400 Description R/W Idle cycles in CS1 and CS5 ...
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Bit Bit Name Initial Value R/W 7 CW3 1 6 CW2 1 Description R/W Idle cycles at continuous access to CS3 and CS7 spaces This bit inserts an idle cycle and negates the CS3 signal to make the bus cycle ...
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Bus State Controller (BSC) Bit Bit Name Initial Value R/W 5 CW1 1 4 CW0 1 3 SW3 1 Rev.4.00 Mar. 27, 2008 Page 150 of 882 REJ09B0108-0400 Description R/W Idle cycles at continuous access to CS1 and CS5 ...
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Bit Bit Name Initial Value R/W 2 SW2 1 1 SW1 1 0 SW0 1 Description CS assert period extension for CS2 and CS6 spaces R/W This bit inserts a cycle to prevent the assert period of RD and WRx ...
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Bus State Controller (BSC) 9.5.3 Wait Control Register 1 (WCR1) WCR1 is a 16-bit readable/writable register that specifies the number of wait cycles (0 to 15) for each CS space. Bit Bit Name Initial Value 15 W33 1 14 ...
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Wait Control Register 2 (WCR2) WCR2 is a 16-bit readable/writable register that specifies the number of access cycles to the CS space in DMA single address mode transfer. Do not perform DMA single address transfer before setting WCR2. Bit ...
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Bus State Controller (BSC) 9.6 Accessing External Space A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct connections. 9.6.1 Basic Timing External access bus cycles are performed in 2 states. Figure ...