HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 753

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.2
Table 23.1 shows the AUD's input/output pins.
Table 23.1 AUD Pin Configuration
23.2.1
• Pins Used in Both Modes
Name
AUD data
AUD reset
AUD mode
AUD clock
AUD sync signal
Pin
AUDMD
AUDRST
Input/Output Pins
Pin Descriptions
Description
The mode is selected by changing the input level at this pin.
Low: Branch trace mode
High: RAM monitor mode
The input at this pin should be changed when AUDRST is low.
The AUD's internal buffers and logic are initialized by inputting a low level to
this pin. When this signal goes low, the AUD enters the reset state and the
AUD's internal buffers and logic are reset. When AUDRST goes high again
after the AUDMD level settles, the AUD starts operating in the selected mode.
Abbreviation
AUDATA3 to
AUDATA0
AUDRST
AUDMD
AUDCK
AUDSYNC
Branch destination address
output
AUD reset input
Sync clock (φ/2) output
Data start position
identification signal output
Branch Trace Mode
Mode select input (L)
Rev.4.00 Mar. 27, 2008 Page 707 of 882
23. Advanced User Debugger (AUD)
Function
RAM Monitor Mode
Monitor address/data
input/output
AUD reset input
Mode select input (H)
Sync clock input
Data start position
identification signal input
REJ09B0108-0400