HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 207

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9. Bus State Controller (BSC)
9.8
Bus Arbitration
This LSI has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device. It also has four internal bus masters, the CPU,
DMAC, DTC, and AUD. The priority for arbitrate the bus mastership between these bus masters
is:
Bus request from external device > AUD > DTC > DMAC > CPU
AUD does not acquire the bus mastership during DTC or DMAC burst transfer; it acquires the bus
mastership after DTC or DMAC burst transfer. AUD has the priority for the bus mastership to
DTC and DMAC if the CPU has the bus mastership. DMAC, continues operating even if DTC
requests the bus mastership during the read or the write period in DMAC dual address mode,
during burst transfer, or during operation in indirect address transfer mode.
A bus request by an external device should be input to the BREQ pin. When the BREQ pin is
asserted, this LSI releases the bus immediately after executing the current bus cycle. The signal
indicating that the bus has been released is output from the BACK pin.
However, the bus arbitration is not performed at the timing between the read cycle and the write
cycle of TAS instruction. In addition, bus arbitration is not performed during bus cycle if the
access size is greater than the data-bus size, for example, when a long-word access is made for an
8-bit size memory.
When an interrupt is generated and the CPU must process this interrupt, the LSI must take back
the bus mastership. For this purpose, this LSI has the IRQOUT pin used for the bus mastership
request signal. Before the LSI takes back the bus mastership, the IRQOUT signal is asserted.
When the IRQOUT signal is asserted, the device that asserted the external bus release request
negates the BREQ signal to release the bus mastership. This allows the bus mastership to return to
the CPU, and the LSI processes the interrupt. The IRQOUT pin is asserted when a cause of
interrupt is generated and the interrupt request level is higher than the interrupt mask bits (I3 to I0)
of the status register (SR).
Figure 9.9 shows a bus mastership release procedure.
Rev.4.00 Mar. 27, 2008 Page 161 of 882
REJ09B0108-0400