HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 185

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.2
Table 9.1 shows the bus state controller pin configuration.
Table 9.1
Note:
Name
Address bus
Data bus
Chip select
Read
Write
Wait
Bus request
Bus acknowledge
*
Input/Output Pins
Pins CS4 to CS7 are available only for the masked ROM version and ROMless version.
Pin Configuration
Abbr.
A21 to A0
D31 to D0
CS0 to CS7* Output Chip select signal indicating the area being
RD
WRHH
WRHL
WRH
WRL
WAIT
BREQ
BACK
I/O
Output Address output (Address bus A21 to A18 pins are
I/O
Output Strobe that indicates the read cycle
Output Strobe that indicates a write cycle to the first byte
Output Strobe that indicates a write cycle to the second
Output Strobe that indicates a write cycle to the third byte
Output Strobe that indicates a write cycle to the fourth byte
Input
Input
Output Bus use enable output
Description
disabled and I/O port function is enabled after
power-on-reset.)
32-bit data bus
accessed
(D31 to D24)
byte (D23 to D16)
(D15 to D8)
(D7 to D0)
Wait state request signal
Bus request input
Rev.4.00 Mar. 27, 2008 Page 139 of 882
9. Bus State Controller (BSC)
REJ09B0108-0400