HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 107

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.1
5.1.1
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority, as shown in table 5.1. When several exception processing sources occur at
once, they are processed according to the priority.
Table 5.1
Notes: 1. Only in the F-ZTAT version.
Exception
Reset
Address
error
Interrupt
Instructions Trap instruction (TRAPA instruction)
2. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
Overview
Types of Exception Processing and Priority
BRAF.
Types of Exception Processing and Priority Order
Source
Power-on reset
Manual reset
CPU address error or AUD address error*
DMAC/DTC address error
NMI
User break
H-UDI
IRQ
On-chip
peripheral
modules:
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delayed
branch instruction*
Section 5 Exception Processing
•
•
•
•
•
•
•
•
•
•
Direct memory access controller (DMAC)
Multifunction timer unit (MTU)
Serial communication interface 0 and 1(SCI0 and SCI1)
A/D converter 0 and 1 (A/D0, A/D1)
Data transfer controller (DTC)
Compare match timer 0 and 1 (CMT0, CMT1)
Watchdog timer (WDT)
Input/output port (I/O) (MTU)
Serial communication interface 2 and 3 (SCI2 and SCI3)
IIC bus interface (IIC)
2
or instructions that rewrite the PC*
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5. Exception Processing
REJ09B0108-0400
Priority
High
Low