HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 548

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
Rev.4.00 Mar. 27, 2008 Page 502 of 882
REJ09B0108-0400
Figure 14.10 Example: Flowchart of Operations in the Master Receive Mode (HNDS = 1)
2
C Bus Interface (IIC) Option
No
No
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Write 0 to BBSY and SCP
Set HNDS = 1 (SCRX)
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Master receive mode
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Final reception?
Read ICDR
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
(ICCR)
End
Yes
Yes
No
Yes
[1] Set receive mode
[2] Dummy read for starting reception (first read)
[5] Read the receive data (second and subsequent read)
[3] Wait for 1 byte of data to be received.
[4] Clear IRIC flag.
[6] Set acknowledge data for the final reception.
[7] Read the receive data. Dummy read for starting
[8] Wait for 1 byte of data to be received.
[10] Read the receive data.
[11] Set stop condition issuance. Generate stop condition.
[9] Clear IRIC flag
(Set IRIC at the rising edge of the 9th cycle of the
clock for the receive frame.)
reception when the first frame is the final receive data.