HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 228

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10. Direct Memory Access Controller (DMAC)
10.4.2
DMA transfer requests are usually generated in either the data transfer source or destination, but
they can also be generated by devices and on-chip peripheral modules that are neither the source
nor the destination. Transfers can be requested in three modes: auto-request, external request, and
on-chip peripheral module request. The request mode is selected in the RS3 to RS0 bits of the
DMA channel control registers_0 to 3 (CHCR_0 to CHCR_3).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of
the DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR_0 to CHCR_3 and
the NMIF and AE bits of DMAOR are all 0).
External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an
external device. Choose one of the modes shown in table 10.2 according to the application system.
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0,
AE = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by
either the falling edge or low level of the signal input with the DS bit of CHCR_0 to CHCR_3 (DS
= 0 is level detection, DS = 1 is edge detection). The source of the transfer request does not have
to be the data transfer source or destination.
Table 10.2 Selecting External Request Modes with RS Bits
Note:
Rev.4.00 Mar. 27, 2008 Page 182 of 882
REJ09B0108-0400
RS3
0
0
0
*
RS2
0
0
0
DMA Transfer Requests
External memory, memory-mapped external device, on-chip memory, and on-chip
peripheral module (excluding DMAC, DTC, BSC, UBC).
RS1
0
1
1
RS0
0
0
1
Address Mode
Dual address
mode
Single address
mode
Single address
mode
Source
Any*
External memory or
memory-mapped
external device
External device with
DACK
Destination
Any*
External device with
DACK
External memory or
memory-mapped
external device