HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 212

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9. Bus State Controller (BSC)
9.10
On-chip peripheral I/O registers are accessed from the bus state controller as shown in table 9.3.
Refer to section 25, List of Registers, for more details.
Table 9.3
9.11
The bus mastership is not released during one bus cycle. For example, when the longword read (or
write) access is performed to the 8-bit normal space, four memory accesses to the 8-bit normal
space are regarded as one bus cycle. In this bus cycle, the bus mastership is not released. In this
case, assuming that one memory access takes two states, the bus mastership is not released in eight
states.
9.12
In this LSI, two words (two instructions) are fetched in one instruction fetch. This also applies to
the cases where program is located in external memory or the bus width of that external memory is
8 or 16 bits.
Also, if the program counter value is the odd word (2n+1) address or the program counter value
before branch is the even word (2n) address, 32 bits (two instructions) including each word
instruction are always fetched.
Rev.4.00 Mar. 27, 2008 Page 166 of 882
REJ09B0108-0400
On-chip
peripheral
module
Connection
bus width
Number of
access
cycles
Access to On-chip Peripheral I/O Registers
Cycles of No-Bus Mastership Release
CPU Operation when Program Is Located in External Memory
SCI
8 bits
2 cyc
Access to On-chip Peripheral I/O Registers
MTU,
POE
16 bits 16 bits 16 bits 16 bits 8 bits
2 cyc
INTC
2 cyc
8 bits
PFC,
PORT
2 cyc
Figure 9.16 One Bus Cycle
mastership is not released
Cycle in which the bus
CMT
2 cyc
8 bits
A/D
3 cyc
8 bits
UBC
16 bits 16 bits 16 bits 16 bits 8 bits
3 cyc
WDT
3 cyc
8 bits
DMAC DTC
3 cyc
3 cyc
IIC
2 cyc
H-UDI
16 bits
2 cyc