DSPIC30F6011-30I/PF Microchip Technology, DSPIC30F6011-30I/PF Datasheet - Page 119

• Manufacturer Part Number: DSPIC30F6011-30I/PF
• Description: IC DSPIC MCU/DSP 132K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6011-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 132KB (44K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 132KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: 3-Wire/CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601130IPF

17.6.2
There is a programmable prescaler with integral values
ranging from 1 to 64, in addition to a fixed divide-by-2
for clock generation. The time quantum (T
unit of time derived from the oscillator period, and is
given by Equation 17-1. .
EQUATION 17-1:
17.6.3
This part of the bit time is used to compensate physical
delay times within the network. These delay times con-
sist of the signal propagation time on the bus line and
the internal delay time of the nodes. The Prop Seg can
be programmed from 1 T
PRSEG<2:0> bits (CiCFG2<2:0>).
17.6.4
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segments are lengthened or short-
ened by resynchronization. The end of the Phase1 Seg
determines the sampling point within a bit period. The
segment is programmable from 1 T
Seg provides delay to the next transmitted data transi-
tion. The segment is programmable from 1 T
or it may be defined to be equal to the greater of
Phase1 Seg or the information processing time (2 T
The Phase1 Seg is initialized by setting bits
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the phase segments:
© 2006 Microchip Technology Inc.
Note:
Prop Seg + Phase1 Seg > = Phase2 Seg
PRESCALER SETTING
F
CANCKS = 0, then F
7.5 MHz.
PROPAGATION SEGMENT
PHASE SEGMENTS
T
CAN
Q
= 2 (BRP<5:0> + 1)/F
must not exceed 30 MHz. If
TIME QUANTUM FOR
CLOCK GENERATION
Q
to 8 T
CY
Q
CAN
Q
must not exceed
to 8 T
dsPIC30F6011/6012/6013/6014
by setting the
Q
) is a fixed
Q
Q
. Phase2
to 8 T
Q
Q
).
,
17.6.5
The sample point is the point of time at which the bus
level is read and interpreted as the value of that respec-
tive bit. The location is at the end of Phase1 Seg. If the
bit timing is slow and contains many T
specify multiple sampling of the bus line at the sample
point. The level determined by the CAN bus then corre-
sponds to the result from the majority decision of three
values. The majority samples are taken at the sample
point and twice before with a distance of T
CAN module allows the user to choose between sam-
pling three times at the same point or once at the same
point, by setting or clearing the SAM bit (CiCFG2<6>).
Typically, the sampling of the bit should take place at
about 60-70% through the bit time, depending on the
system parameters.
17.6.6
To compensate for phase shifts between the oscillator
frequencies of the different bus stations, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time (Synchro-
nous Segment). The circuit will then adjust the values
of Phase1 Seg and Phase2 Seg. There are 2
mechanisms used to synchronize.
17.6.6.1
Hard synchronization is only done whenever there is a
‘recessive’ to ‘dominant’ edge during bus Idle indicating
the start of a message. After hard synchronization, the
bit time counters are restarted with the Sync Seg. Hard
synchronization forces the edge which has caused the
hard synchronization to lie within the synchronization
segment of the restarted bit time. If a hard synchroniza-
tion is done, there will not be a resynchronization within
that bit time.
17.6.6.2
As a result of resynchronization, Phase1 Seg may be
lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase
buffer segment has an upper bound known as the syn-
chronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-
chronization jump width will be added to Phase1 Seg or
subtracted from Phase2 Seg. The resynchronization
jump width is programmable between 1 T
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
Phase2 Seg > Synchronization Jump Width
SAMPLE POINT
SYNCHRONIZATION
Hard Synchronization
Resynchronization
DS70117F-page 117
Q
, it is possible to
Q
and 4 T
Q
/2. The
Q
.