DSPIC30F6011-30I/PF Microchip Technology, DSPIC30F6011-30I/PF Datasheet - Page 221

• Manufacturer Part Number: DSPIC30F6011-30I/PF
• Description: IC DSPIC MCU/DSP 132K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6011-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 132KB (44K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 132KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: 3-Wire/CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F601130IPF

F
Fast Context Saving............................................................ 49
Flash Program Memory ...................................................... 51
I
I/O Pin Specifications
I/O Ports .............................................................................. 63
I
I
I
I
I
I
Idle Current (I
In-Circuit Serial Programming (ICSP) ......................... 51, 145
Input Capture (CAPX) Timing Characteristics .................. 191
Input Capture Module ......................................................... 83
Input Capture Operation During Sleep and Idle Modes ...... 84
Input Capture Timing Requirements ................................. 191
© 2006 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 97
C 7-bit Slave Mode Operation .......................................... 97
C Master Mode Operation ................................................ 99
C Master Mode Support ................................................... 99
C Module .......................................................................... 95
S Mode Operation .......................................................... 133
Control Registers ........................................................ 52
Input .......................................................................... 178
Output ....................................................................... 179
Parallel (PIO) .............................................................. 63
Reception.................................................................... 98
Transmission............................................................... 97
Reception.................................................................... 97
Transmission............................................................... 97
Baud Rate Generator................................................ 100
Clock Arbitration........................................................ 100
Multi-Master Communication, Bus Collision
Reception.................................................................... 99
Transmission............................................................... 99
Addresses ................................................................... 97
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................... 99
Interrupts..................................................................... 98
IPMI Support ............................................................... 99
Operating Function Description .................................. 95
Operation During CPU Sleep and Idle Modes .......... 100
Pin Configuration ........................................................ 95
Programmer’s Model................................................... 95
Register Map............................................................. 101
Registers..................................................................... 95
Slope Control .............................................................. 99
Software Controlled Clock Stretching (STREN = 1).... 98
Various Modes ............................................................ 95
Data Justification....................................................... 133
Frame and Data Word Length Selection................... 133
Interrupts..................................................................... 84
Register Map............................................................... 85
CPU Idle Mode............................................................ 84
CPU Sleep Mode ........................................................ 84
NVMADR ............................................................ 52
NVMADRU.......................................................... 52
NVMCON ............................................................ 52
NVMKEY............................................................. 52
and Bus Arbitration ........................................... 100
Master Mode ..................................................... 201
Slave Mode ....................................................... 203
Master Mode ..................................................... 202
Slave Mode ....................................................... 203
Master Mode ..................................................... 201
Slave Mode ....................................................... 203
IDLE
) ............................................................ 176
dsPIC30F6011A/6012A/6013A/6014A
Input Change Notification Module....................................... 67
Instruction Addressing Modes ............................................ 39
Instruction Set
Internet Address ............................................................... 223
Interrupt Controller
Interrupt Priority .................................................................. 46
Interrupt Sequence ............................................................. 48
Interrupts ............................................................................ 45
L
Load Conditions................................................................ 182
Low Voltage Detect (LVD) ................................................ 156
Low-Voltage Detect Characteristics.................................. 179
LVDL Characteristics ........................................................ 180
M
Memory Organization ......................................................... 25
Microchip Internet Web Site.............................................. 223
Modes of Operation
Modulo Addressing ............................................................. 40
MPLAB ASM30 Assembler, Linker, Librarian ................... 170
MPLAB ICD 2 In-Circuit Debugger ................................... 171
MPLAB ICE 2000 High-Performance Universal
MPLAB Integrated Development Environment Software.. 169
MPLAB PM3 Device Programmer .................................... 171
MPLAB REAL ICE In-Circuit Emulator System ................ 171
MPLINK Object Linker/MPLIB Object Librarian ................ 170
N
NVM
Register Map for dsPIC30F6011/6012 (Bits 15-8) ..... 67
Register Map for dsPIC30F6011/6012 (Bits 7-0) ....... 67
Register Map for dsPIC30F6013/6014 (Bits 15-8) ..... 67
Register Map for dsPIC30F6013/6014 (Bits 7-0) ....... 67
File Register Instructions ............................................ 39
Fundamental Modes Supported ................................. 39
MAC Instructions ........................................................ 40
MCU Instructions ........................................................ 39
Move and Accumulator Instructions ........................... 40
Other Instructions ....................................................... 40
Overview................................................................... 164
Summary .................................................................. 161
Register Map .............................................................. 50
Interrupt Stack Frame................................................. 49
Core Register Map ..................................................... 35
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback .................................................................. 113
Normal Operation ..................................................... 113
Applicability................................................................. 42
Operation Example..................................................... 41
Start and End Address ............................................... 41
W Address Register Selection.................................... 41
In-Circuit Emulator.................................................... 171
Register Map .............................................................. 55
DS70143C-page 219