ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 106

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3.5
13.3.6
13.3.7
106
ATtiny25/45/85
OCR1C – Timer/Counter1 Output Compare Register C
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare
register C - OCR1C that is an 8-bit read/write register. This register has the same function as the
Output Compare Register B in ATtiny15.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector
$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is
executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the
Timer/Counter Interrupt Flag Register - TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit
0x2D
Read/Write
Initial value
Bit
0x39
Read/Write
Initial value
Bit
0x38
Read/Write
Initial value
MSB
R/W
R
R
7
–
0
7
–
0
7
1
OCIE1A
OCF1A
R/W
R/W
R/W
6
1
6
0
6
0
OCIE1B
R/W
OCF1B
5
1
R/W
R/W
5
0
5
0
R/W
OCIE0A
4
1
R/W
OCF0A
4
0
R/W
4
0
R/W
3
1
OCIE0B
OCF0B
R/W
R/W
3
0
3
0
R/W
2
1
TOIE1
TOV1
R/W
R/W
2
0
2
0
R/W
1
1
TOIE0
TOV0
R/W
R/W
1
0
1
0
LSB
R/W
0
1
2586M–AVR–07/10
R
0
–
0
R
0
–
0
OCR1C
TIMSK
TIFR