ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 89

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.1
12.2.2
2586M–AVR–07/10
Timer/Counter1 Initialization for Asynchronous Mode
Timer/Counter1 in PWM Mode
values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to
500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.
To set Timer/Counter1 in asynchronous mode first enable PLL and then wait 100 µs for PLL to
stabilize. Next, poll the PLOCK bit until it is set and then set the PCKE bit.
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C -
OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the
PB1(OC1A) and PB4(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB3(OC1B). As
default non-overlapping times for complementary output pairs are zero, but they can be inserted
using a Dead Time Generator (see description on page 100).
Figure 12-4. The PWM Output Pair
When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs
are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the
Timer/Counter1 Control Register A - TCCR1, as shown in
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output
compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set
an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.
Table 12-1.
Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data
value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B
when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM
pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See
example.
COM1x1
0
0
1
1
PWM1x
PWM1x
Compare Mode Select in PWM Mode
t
non-overlap
COM1x0
0
1
0
1
=0
Effect on Output Compare Pins
OC1x not connected.
OC1x not connected.
OC1x cleared on compare match. Set whenTCNT1 = $00.
OC1x set on compare match. Cleared when TCNT1 = $00.
OC1x cleared on compare match. Set when TCNT1 = $00.
OC1x not connected.
OC1x Set on compare match. Cleared when TCNT1= $00.
OC1x not connected.
t
non-overlap
=0
x = A or B
Table
12-1.
Figure 12-5
for an
89