ATTINY25-20SUR Atmel, ATTINY25-20SUR Datasheet - Page 84

• Manufacturer Part Number: ATTINY25-20SUR
• Description: MCU AVR 2KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY25-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.9.6
11.9.7
11.9.8
84
ATtiny25/45/85
OCR0B – Output Compare Register B
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 4 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
Bit
0x39
Read/Write
Initial Value
Bit
0x28
Read/Write
Initial Value
Bit
0x38
Read/Write
Initial Value
R/W
7
–
R
0
R
7
0
7
–
0
OCIE1A
OCF1A
R/W
R/W
R/W
6
0
6
0
6
0
OCIE1B
OCF1B
R/W
R/W
R/W
5
0
5
0
5
0
OCIE0A
OCF0A
R/W
R/W
R/W
4
0
4
0
4
0
OCR0B[7:0]
OCIE0B
OCF0B
R/W
R/W
R/W
3
0
3
0
3
0
TOIE1
TOV1
R/W
R/W
R/W
2
0
2
0
2
0
TOIE0
TOV0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R
0
0
R
0
–
0
0
–
0
2586M–AVR–07/10
OCR0B
TIMSK
TIFR